Design Unit List

Here is a list of all design unit members with links to the Entities and Packages they belong to:

daq_header	Functions used in DAQ modules
abort_buffer	DPBRAM for abort logic
abort_buffer.abort_buffer_a	BRAM primitive instantiation
abort_controller	Beam abort logic
abort_controller.abort_controller_arc	Beam abort logic
ADDSUB48	Virtex-4 DSP48 Core Wrapper
ADDSUB48.ADDSUB48_ARCH	Virtex-4 DSP48 Core Wrapper
auto_receiver	Receives packets from EMAC & decodes packets
auto_receiver.auto_receiver_arc	Receives packets from EMAC & decodes packets
bcm_aaa	Top module of BCM AAA design
bcm_aaa.bcm_aaa_arc	Top module of BCM AAA design
bcm_emac_fifo	Wrapper file for FIFO core for Ethernet TX
bcm_emac_fifo.bcm_emac_fifo_a	Wrapper file for FIFO core for Ethernet TX
bcm_emac_fifo_rx	Wrapper file for FIFO core for Ethernet RX
bcm_emac_fifo_rx.bcm_emac_fifo_rx_a	Wrapper file for FIFO core for Ethernet RX
bcm_rod	ROD formatter top module
bcm_rod.bcm_rod_arc	Structural description of ROD formatter
bcm_rod_dp_ram	DPRAM
bcm_rod_dp_ram.bcm_rod_dp_ram_a	Instantiates DPRAM primitive
bcm_rod_dp_updown_counter	Up-Down Counter
bcm_rod_dp_updown_counter.bcm_rod_dp_updown_counter_arc	Up-down counter
bcm_rod_formatter	ROD formatter
bcm_rod_formatter.bcm_rod_formatter_arc	ROD formatter main FSM
bcm_rod_ram	DPRAM wrapper
bcm_rod_ram.bcm_rod_ram_arc	DPRAM wrapper with RAM support logic
bcm_rod_slink	S-Link interface
bcm_rod_slink.bcm_rod_slink_arc	S-Link interface
bcm_rod_treadmil	ROD treadmill
bcm_rod_treadmil.bcm_rod_treadmil_arc	ROD treadmill
bcm_signal_delay	Flexible shift-register as delay unit
bcm_signal_delay.bcm_signal_delay_arc	Runtime adjustable shift register, min delay = 8 clock cycles
bcm_signal_delay_vec	Flexible shift-register as delay unit
bcm_signal_delay_vec.bcm_signal_delay_vec_arc	Flexible shift-register as delay unit
BID_cnt	Bunch-Counter
BID_cnt.BID_cnt_arc	Bunch-Counter
bridge	Top module of SATA
bridge.bridge_arc	Top module of SATA
buffer_3ST	Tri-State Buffer
buffer_3ST.buffer_3ST_arc	Tri-State Buffer
bunchcycle	Collects pulse information and groups it per bunch crossing
bunchcycle.bunchcycle_arc	Collects pulse information and groups it per bunch crossing
busy	Busy module
busy.busy_arc	Busy module
cal	Calculate pulse widths
cal.cal_arc	Calculate pulse widths
cal_block_v1_4_1	RocketIO calibration module
cal_block_v1_4_1.rtl	RocketIO calibration module
cibu_comm	Interface to CIBU (User Interface Console to Beam Interlock System)
cibu_comm.cibu_comm_arc	Interface to CIBU (User Interface Console to Beam Interlock System)
clock_divider	Prescaler
clock_divider.clock_divider_arc	Prescaler
clocks	Central clock module
clocks.coldplay	Central clock module
cnt_ddr2_rd	Counter for accesses to DDR2
cnt_ddr2_rd.cnt_ddr2_rd_arc	Counter for accesses to DDR2
cnt_ddr_rd	Counter for accesses to DDR
cnt_ddr_rd.cnt_ddr_rd_arc	Counter for accesses to DDR
command_decoder	Pc-controlled module inside the FPGA
command_decoder.command_decoder_arc	Decoder for commands from PC
comparator4	4-Input greatest value selector
comparator4.comparator4_arc	4-Input greatest value selector
comparator_v9_0	Greater-than Comparator Core
comparator_v9_0.comparator_v9_0_a	Comparator core instantation
ctp_comm	Interface to CTP (Central Trigger Processor)
ctp_comm.ctp_comm_arc	Interface to CTP (Central Trigger Processor)
ctp_logic	Top module of logic for CTP bits
ctp_logic.ctp_logic_arc	CTP logic
daq_header	Functions used in DAQ modules
daqrio_top	Top module of 2 full RIO chains
daqrio_top.daqrio_top_arc	Structural description of RocketIO readout
ddr2_chksum_cal	Running UDP checksum calculation DDR2
ddr2_chksum_cal.ddr2_dsp_chksum_cal_arc	Running UDP checksum calculation DDR2
ddr2_data_buffer	Interface between DAQ & DDR2
ddr2_data_buffer.ddr2_data_buffer_arc	Interface between DAQ & DDR2, buffer with circular addressing
ddr2_mem	Structure of DDR2 Controller
ddr2_mem.arc_ddr2_mem	Structure of DDR2 Controller
ddr2_mem_backend_fifos_0	DDR2 Back-End FIFOs
ddr2_mem_backend_fifos_0.arc_backend_fifos	DDR2 Back-End FIFOs
ddr2_mem_controller_iobs_0	Control signal IOBs
ddr2_mem_controller_iobs_0.arc_controller_iobs	Control signal IOBs
ddr2_mem_data_path_0	Calibration structure for data
ddr2_mem_data_path_0.arc_data_path	Calibration structure for data
ddr2_mem_data_path_iobs_0	Datapath IOBs
ddr2_mem_data_path_iobs_0.arc_data_path_iobs	Datapath IOBs
ddr2_mem_data_tap_inc	Tap logic
ddr2_mem_data_tap_inc.arc_data_tap_inc	Tap logic
ddr2_mem_data_write_0	Write data organizer
ddr2_mem_data_write_0.arc_data_write	Write data organizer
ddr2_mem_ddr2_controller_0	Main RAM controller module
ddr2_mem_ddr2_controller_0.arc_controller	Main RAM controller module
ddr2_mem_idelay_ctrl	IDELAYCTRL primitive
ddr2_mem_idelay_ctrl.arc_idelay_ctrl	IDELAYCTRL instantiation
ddr2_mem_infrastructure	Services for DDR2 memory controller
ddr2_mem_infrastructure.arc_infrastructure	Services for DDR2 memory controller
ddr2_mem_infrastructure_iobs_0	DDR clock IOBs
ddr2_mem_infrastructure_iobs_0.arc_infrastructure_iobs	DDR Clock IOBs
ddr2_mem_iobs_0	DDR2 IOBs
ddr2_mem_iobs_0.arc_iobs	DDR2 IOBs
ddr2_mem_parameters_0	Header file for DDR2 RAM controller
ddr2_mem_pattern_compare8	DDR2 pattern compare
ddr2_mem_pattern_compare8.arc_pattern_compare	DDR2 pattern compare
ddr2_mem_RAM_D_0	DistRAM to buffer data
ddr2_mem_RAM_D_0.arc_RAM	DistRAM to buffer data
ddr2_mem_rd_data_0	Read datapath
ddr2_mem_rd_data_0.arc_rd_data	Read datapath
ddr2_mem_rd_data_fifo_0	DistRAM for read data
ddr2_mem_rd_data_fifo_0.arc_rd_data_fifo	DistRAM for read data
ddr2_mem_rd_wr_addr_fifo_0	FIFO for read/write address
ddr2_mem_rd_wr_addr_fifo_0.arc_rd_wr_addr_fifo	FIFO for read/write address
ddr2_mem_tap_ctrl	Tap control logic
ddr2_mem_tap_ctrl.arch	Tap control logic
ddr2_mem_tap_logic_0	Data tap module
ddr2_mem_tap_logic_0.arc_tap_logic	Data tap module
ddr2_mem_top_0	Top module of DDR2 RAM controller
ddr2_mem_top_0.arc_top	Top module of DDR2 RAM controller
ddr2_mem_user_interface_0	DDR2 controller user interface
ddr2_mem_user_interface_0.user_interface_arc	DDR2 controller user interface
ddr2_mem_v4_dm_iob	This module places the data mask signals into the IOBs
ddr2_mem_v4_dm_iob.arc_v4_dm_iob	DDR2 data mask IOBs
ddr2_mem_v4_dq_iob	DDR2 data IOBs
ddr2_mem_v4_dq_iob.arc_v4_dq_iob	DDR2 data IOBs
ddr2_mem_v4_dqs_iob	DDR2 data strobe IOBs
ddr2_mem_v4_dqs_iob.arc_v4_dqs_iob	DDR2 data strobe IOBs
ddr2_mem_wr_data_fifo_16	Write data FIFO
ddr2_mem_wr_data_fifo_16.arc_wr_data_fifo_16	Write data FIFO
ddr2_usr_be	Top module of DDR2 RAM controller
ddr2_usr_be.ddr2_usr_be_arc	Top module of DDR2 RAM controller
ddr_chksum_accu	32-bit DSP accumulator
ddr_chksum_accu.BEHAVIORAL	32-bit DSP accumulator
ddr_chksum_adder	32-bit DSP adder
ddr_chksum_adder.BEHAVIORAL	32-bit DSP adder
ddr_chksum_cal	Running UDP checksum calculation DDR
ddr_chksum_cal.ddr_dsp_chksum_cal_arc	Running UDP checksum calculation DDR
ddr_data_buffer	Interface between DAQ & DDR
ddr_data_buffer.ddr_data_buffer_arc	Interface between DAQ & DDR
ddr_eth_buf	Buffer between DDR & EMAC
ddr_eth_buf.ddr_eth_buf_arc	Buffer between DDR & EMAC
ddreth_buf	Wrapper for BRAM Buffer between DDR and Ethernet
ddreth_buf.ddreth_buf_a	Wrapper for BRAM Buffer between DDR and Ethernet
delay	Delay unit
delay.delay_arc	Delay unit
delay_adj	Fine delay for 2 RocketIO channels
delay_adj.delay_adj_arc	Fine delay for 2 RocketIO channels
delta_t_ac_top	Top module of time window & coincidence logic
delta_t_ac_top.double	Register 2 hits within time window
delta_t_ac_top.one_to_one	1-1 Coincidence within time window
delta_t_ac_top.single	Register hit within time window
delta_t_ac_top.two_to_two	2-2 Coincidence within time window
division	Division by constant power of two
division.division_arc	Division by constant power of two
dss_comm	Interface to DSS (Detector Safety System) This entity provides two redundant signals to the DSS, 1 Warning and 1 Abort. Outputs are also settable from the outside
dss_comm.dss_comm_arc	Interface to DSS (Detector Safety System) This entity provides the two redundant signals to the DSS. Outputs are settable from the outside
edge	Standard rising edge detection
edge.edge_arc	Standard rising edge detection
edge_det	Data edge detection
edge_det.new2	Data edge detection
edge_fal	Standard falling edge detection
edge_fal.edge_fal_arc	Standard falling edge detection
eth_buf	Buffer between DDR2 and EMAC for clock domain crossing
eth_buf.eth_buf_arc	Address generation for buffer
ethbuf	Wrapper for DPRAM Buffer core
ethbuf.ethbuf_arc	DPBRAM instantiation
ethernet_top	Top module of Ethernet design part, both RX & TX
ethernet_top.ethernet_top_arc	Main logic for sending data & interfacing between EMAC & memories
EVENT_cnt	ATLAS Level-1 Event Counter
EVENT_cnt.EVENT_cnt_arc	ATLAS Level-1 Event Counter
extend_test	Extending a pulse
extend_test.extend_test_arc	Extending a pulse
generic_shift_reg	Generic shift register. Width and depth adjustable at compile-time
generic_shift_reg.generic_shift_reg_arc	Generic shift register. Width and depth adjustable at compile-time
GT11_INIT_RX	Initializer for RocketIO RX
GT11_INIT_RX.rtl	Initialization logic for RocketIO RX
GT11_INIT_TX	Initializer for RocketIO TX
GT11_INIT_TX.rtl	Initialization logic for RocketIO TX
incrementer	32-bit incrementer with synchronous reset and latched output
incrementer.incrementer_arc	32-bit incrementer with synchronous reset and latched output
intime	Narrow in-time time window
intime.intime_arc	Narrow in-time time window
ipmac	Header with IP & MAC addresses
l1a_fifo	FIFO core for L1As
l1a_fifo.l1a_fifo_a	FIFO core for L1As
LCD	LCD wrapper
LCD.LCD_arc	LCD wrapper
lcd_characters	Constants declaration
lcd_commander	Commander for LCD
lcd_controller	LCD controller
LFSR14_23A3	Linear feedback shift register (LFSR)
LFSR14_23A3.RTL	Linear feedback shift register (LFSR)
loop_cnt	Continous counter, 32 bit
loop_cnt.loop_cnt_arc	Continous counter, 32 bit
loop_cnt_sh	Continous counter, 6 bit
loop_cnt_sh.loop_cnt_sh_arc	Continous counter, 6 bit
ltp_comm	Interface to LTP (Local Trigger Processor)
ltp_comm.ltp_comm_arc	Interface to LTP (Local Trigger Processor)
lvl1_buf	Buffer for Level-1 TDAQ data
lvl1_buf.lvl1_buf_arc	Buffer for Level-1 TDAQ data
lvl1_circ_buffer	DPBRAM Buffer, can store one full turn
lvl1_circ_buffer.lvl1_circ_buffer_a	DPBRAM instantiation
main_components	Declaration of all major components, global constants & types
mem_interface_top_idelay_ctrl	Virtex-4 IDELAYCTRL Wrapper
mem_interface_top_idelay_ctrl.arch	Virtex-4 IDELAYCTRL Wrapper
mem_interface_top_infrastructure	DCM for DDR specific clocks
mem_interface_top_infrastructure.arch	DCM for DDR specific clocks
mem_interface_top_parameters_0	Header file for DDR RAM controller
MGT_CLOCK_MODULE	Wrapper for RocketIO clock module
MGT_CLOCK_MODULE.RTL	Wrapper for RocketIO clock module
ncm_temac	Interface to HW MAC
ncm_temac.ncm_temac_arc	Interface to HW MAC
onescompaccu	Accu with Carry Look-Ahead Adder
onescompaccu.onescompaccu_arc	Logic around CLA-Adder
onescomplementadder	Carry Look-Ahead Full-Adder
onescomplementadder.onescomplementadder_arc	Carry Look-Ahead Full-Adder
ORBIT_cnt	Counter for LHC Machine Turns
ORBIT_cnt.ORBIT_cnt_arc	Counter for LHC Machine Turns
period_check	Check the period of signal
period_check.period_check_arc	Check the period of signal
pmdelay	Variable Post-Mortem layoff - orbit delay
pmdelay.pmdelay_arc	Variable Post-Mortem layoff - orbit delay
prescaler	Simple Prescaler
prescaler.prescaler_arc	Simple Prescaler
proc_data_buf	Dual-Port BRAM Buffer customized for proc data
proc_data_buf.proc_data_buf_a	DPBRAM instantiation
proc_data_emul	Pattern generator to fill proc data buffers
proc_data_emul.proc_data_emul_arc	Pattern generator to fill proc data buffers
ram_user_backend	Top module of DDR RAM controller
ram_user_backend.ram_user_backend_arc	Control of interface to external RAM
raw_buffer	Wrapper for BRAM Buffer between RIOs and DDR2
raw_buffer.raw_buffer_a	Wrapper for BRAM Buffer between RIOs and DDR2
raw_data_emul	Pattern generator to fill raw data buffers
raw_data_emul.raw_data_emul_arc	Pattern generator to fill raw data buffers
RIO	RocketIO wrapper
rio2mem	Contains all major design modules (RAMs, RIO, EMAC)
rio2mem.rio2mem_arc	Contains all major design modules (RAMs, RIO, EMAC)
RIO.RIO_arc	Instantiation of RocketIO primitive
rio_rxtx	DAQ-RocketIO wrapper and support logic
rio_rxtx.rio_rxtx_arc	DAQ-RocketIO wrapper and support logic
riocheck	Error detection module for RocketIOs, currently unused
riocheck.riocheck_arc	Error detection module for RocketIOs, currently unused
rios_all	Combination of RocketIOs for each side of the IP
rios_all.rios_all_arc	Combination of RocketIOs for each side of the IP
ROCKETIO_SATA	SATA RocketIO wrapper
ROCKETIO_SATA.ROCKETIO_SATA_arc	RocketIO primitive instantiation
sata	SATA wrapper
sata.sata_arc	SATA wrapper
sata_cal_block_v1_4_1	Calibration of sata clocks
sata_cal_block_v1_4_1.rtl	Calibration logic for SATA RocketIO clocks
sata_GT11_INIT_RX	RIO-RX initializer
sata_GT11_INIT_RX.rtl	RIO-RX initializer
sata_GT11_INIT_TX	RIO-TX initializer
sata_GT11_INIT_TX.rtl	RIO-TX initializer
shift_reg	Adjustable 32-bit wide shift register
shift_reg.shift_reg_a	DPBRAM instantiation
side_4rios	Combination of 2 RocketIO-pairs
side_4rios.side_4rios_arc	Combination of 2 RocketIO-pairs
statistics	Determines minimum, maximum and average of a series of input values
statistics.statistics_arc	Determines minimum, maximum and average of a series of input values
status_collector	Data collector for DCS status messages
status_collector.status_collector_arc	Data collector for status messages
tdaq_collector	Data collector for TDAQ status messages
tdaq_collector.tdaq_collector_arc	Data collector for status messages
temac_controller	Support logic for EMAC
temac_controller.temac_controller_arc	Support logic for TEMAC
timewindow	Apply time window to 1 channel
timewindow.timewindow_arc	Apply time window to 1 channel
udp_addresses	Declarations of constants, types & functions for Ethernet modules
univibrator	Univibrator
univibrator.univibrator_arc	Univibrator
xtemac	Virtex-4 FX Ethernet MAC Wrapper
xtemac.WRAPPER	EMAC Wrapper