daqrio_top Entity Reference
Top module of 2 full RIO chains. More...
Inheritance diagram for daqrio_top:
Collaboration diagram for daqrio_top:
Architectures | |
| daqrio_top_arc | Architecture |
| Structural description of RocketIO readout. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| WORK | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| daq_header | Package <daq_header> |
Generics | |
| PATTERN | std_logic_vector ( 31 downto 0 ) := " 11110000111100001111000011110000 " |
| external XOR pattern | |
Ports | |
| SET_SHIFT | in std_logic_vector ( 7 downto 0 ) |
| set reco pattern shift | |
| CALIB | in std_logic |
| initiate pattern reco, both channels | |
| CAL1 | in std_logic |
| initiate pattern reco, channel 1 | |
| CAL2 | in std_logic |
| initiate pattern reco, channel 2 | |
| CHECK_1 | out std_logic |
| reco check with 32-bit OR, ch1 | |
| CHECK_2 | out std_logic |
| reco check with 32-bit OR, ch2 | |
| RES | in std_logic |
| reset | |
| REF | in std_logic |
| RocketIO reference clock, 160 MHz. | |
| PAR | in std_logic |
| parallel clock, 80 MHz | |
| BC | in std_logic |
| bunch clock, 40 MHz | |
| EN | in std_logic |
| enable | |
| COARSE_TIME_1 | in std_logic_vector ( 7 downto 0 ) |
| coarse delay, ch1 | |
| COARSE_TIME_2 | in std_logic_vector ( 7 downto 0 ) |
| coarse delay, ch2 | |
| ADJUST_TIME_1 | in integer range 0 to 32 := 0 |
| fine delay, bottom half, ch1 | |
| ADJUST_TIME_2 | in integer range 0 to 32 := 0 |
| fine delay, bottom half, ch2 | |
| ADJUST_TIME_12 | in integer range 0 to 32 := 0 |
| fine delay, top half, ch1 | |
| ADJUST_TIME_22 | in integer range 0 to 32 := 0 |
| fine delay, top half, ch1 | |
| TX_SYSTEM_RESET_IN | in std_logic |
| tx reset | |
| RX_SYSTEM_RESET_IN | in std_logic |
| rx reset | |
| MGT0_RXLOCK_OUT | out std_logic |
| PLL lock flag. | |
| MGT0_TXLOCK_OUT | out std_logic |
| PLL lock flag. | |
| MGT1_RXLOCK_OUT | out std_logic |
| PLL lock flag. | |
| MGT1_TXLOCK_OUT | out std_logic |
| PLL lock flag. | |
| RX1N_IN | in std_logic_vector ( 1 downto 0 ) |
| serial rx data in | |
| RX1P_IN | in std_logic_vector ( 1 downto 0 ) |
| serial rx data in | |
| TX1N_OUT | out std_logic_vector ( 1 downto 0 ) |
| serial tx data out | |
| TX1P_OUT | out std_logic_vector ( 1 downto 0 ) |
| serial tx data out | |
| RX_READY_FLAG | out std_logic |
| flag rx reset procedure finished | |
| TX_READY_FLAG | out std_logic |
| flag tx reset procedure finished | |
| PULSE_OUT_P | out std_logic |
| output pulse pos for external XOR | |
| SUM_RIS_1 | out std_logic_vector ( 7 downto 0 ) |
| multiplicity rising edge ch1 | |
| SUM_FAL_1 | out std_logic_vector ( 7 downto 0 ) |
| multiplicity falling edge ch1 | |
| T1_1 | out std_logic_vector ( 7 downto 0 ) |
| rising edge 1, ch1 | |
| T2_1 | out std_logic_vector ( 7 downto 0 ) |
| rising edge 2, ch1 | |
| T3_1 | out std_logic_vector ( 7 downto 0 ) |
| rising edge 3, ch1 | |
| W1_1 | out std_logic_vector ( 7 downto 0 ) |
| falling edge 1, ch1 | |
| W2_1 | out std_logic_vector ( 7 downto 0 ) |
| falling edge 2, ch1 | |
| W3_1 | out std_logic_vector ( 7 downto 0 ) |
| falling edge 3, ch1 | |
| STATUS_T1_1 | out std_logic |
| valid T1_1 | |
| STATUS_T2_1 | out std_logic |
| valid T2_1 | |
| STATUS_T3_1 | out std_logic |
| valid T3_1 | |
| STATUS_W1_1 | out std_logic |
| valid W1_1 | |
| STATUS_W2_1 | out std_logic |
| valid W2_1 | |
| STATUS_W3_1 | out std_logic |
| valid W3_1 | |
| OVERFLOW_1 | out std_logic |
| cycle overspill flag, ch1 | |
| SUM_RIS_2 | out std_logic_vector ( 7 downto 0 ) |
| multiplicity rising edge ch2 | |
| SUM_FAL_2 | out std_logic_vector ( 7 downto 0 ) |
| multiplicity falling edge ch2 | |
| T1_2 | out std_logic_vector ( 7 downto 0 ) |
| rising edge 1, ch2 | |
| T2_2 | out std_logic_vector ( 7 downto 0 ) |
| rising edge 2, ch2 | |
| T3_2 | out std_logic_vector ( 7 downto 0 ) |
| rising edge 3, ch2 | |
| W1_2 | out std_logic_vector ( 7 downto 0 ) |
| falling edge 1, ch2 | |
| W2_2 | out std_logic_vector ( 7 downto 0 ) |
| falling edge 2, ch2 | |
| W3_2 | out std_logic_vector ( 7 downto 0 ) |
| falling edge 3, ch2 | |
| STATUS_T1_2 | out std_logic |
| valid T1_2 | |
| STATUS_T2_2 | out std_logic |
| valid T2_2 | |
| STATUS_T3_2 | out std_logic |
| valid T3_2 | |
| STATUS_W1_2 | out std_logic |
| valid W1_2 | |
| STATUS_W2_2 | out std_logic |
| valid W2_2 | |
| STATUS_W3_2 | out std_logic |
| valid W3_2 | |
| OVERFLOW_2 | out std_logic |
| cycle overspill flag, ch1 | |
| MASK_1 | out std_logic |
| mask ch1 | |
| MASK_2 | out std_logic |
| mask ch1 | |
| CALIB_DONE | out std_logic |
| reco done flag | |
| RAW_DATA1 | out std_logic_vector ( 31 downto 0 ) |
| raw data out, ch1 | |
| RAW_DATA2 | out std_logic_vector ( 31 downto 0 ) |
| raw data out, ch2 | |
Detailed Description
Top module of 2 full RIO chains.In this entity all submodules of the full read-out and DAQ chain are instantiated for a RocketIO pair.
Definition at line 38 of file daqrio_top.vhd.
Member Data Documentation
ADJUST_TIME_1 in integer range 0 to 32 := 0 [Port] |
ADJUST_TIME_12 in integer range 0 to 32 := 0 [Port] |
ADJUST_TIME_2 in integer range 0 to 32 := 0 [Port] |
ADJUST_TIME_22 in integer range 0 to 32 := 0 [Port] |
BC in std_logic [Port] |
CAL1 in std_logic [Port] |
CAL2 in std_logic [Port] |
CALIB in std_logic [Port] |
CALIB_DONE out std_logic [Port] |
CHECK_1 out std_logic [Port] |
CHECK_2 out std_logic [Port] |
COARSE_TIME_1 in std_logic_vector ( 7 downto 0 ) [Port] |
COARSE_TIME_2 in std_logic_vector ( 7 downto 0 ) [Port] |
EN in std_logic [Port] |
ieee library [Library] |
MASK_1 out std_logic [Port] |
MASK_2 out std_logic [Port] |
MGT0_RXLOCK_OUT out std_logic [Port] |
MGT0_TXLOCK_OUT out std_logic [Port] |
MGT1_RXLOCK_OUT out std_logic [Port] |
MGT1_TXLOCK_OUT out std_logic [Port] |
OVERFLOW_1 out std_logic [Port] |
OVERFLOW_2 out std_logic [Port] |
PAR in std_logic [Port] |
PATTERN std_logic_vector ( 31 downto 0 ) := " 11110000111100001111000011110000 " [Generic] |
PULSE_OUT_P out std_logic [Port] |
RAW_DATA1 out std_logic_vector ( 31 downto 0 ) [Port] |
RAW_DATA2 out std_logic_vector ( 31 downto 0 ) [Port] |
REF in std_logic [Port] |
RES in std_logic [Port] |
RX1N_IN in std_logic_vector ( 1 downto 0 ) [Port] |
RX1P_IN in std_logic_vector ( 1 downto 0 ) [Port] |
RX_READY_FLAG out std_logic [Port] |
RX_SYSTEM_RESET_IN in std_logic [Port] |
SET_SHIFT in std_logic_vector ( 7 downto 0 ) [Port] |
STATUS_T1_1 out std_logic [Port] |
STATUS_T1_2 out std_logic [Port] |
STATUS_T2_1 out std_logic [Port] |
STATUS_T2_2 out std_logic [Port] |
STATUS_T3_1 out std_logic [Port] |
STATUS_T3_2 out std_logic [Port] |
STATUS_W1_1 out std_logic [Port] |
STATUS_W1_2 out std_logic [Port] |
STATUS_W2_1 out std_logic [Port] |
STATUS_W2_2 out std_logic [Port] |
STATUS_W3_1 out std_logic [Port] |
STATUS_W3_2 out std_logic [Port] |
std_logic_1164 package [Package] |
std_logic_arith package [Package] |
arithmetic operations on std_logic datatypes, see file
Definition at line 29 of file daqrio_top.vhd.
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 31 of file daqrio_top.vhd.
SUM_FAL_1 out std_logic_vector ( 7 downto 0 ) [Port] |
SUM_FAL_2 out std_logic_vector ( 7 downto 0 ) [Port] |
SUM_RIS_1 out std_logic_vector ( 7 downto 0 ) [Port] |
SUM_RIS_2 out std_logic_vector ( 7 downto 0 ) [Port] |
T1_1 out std_logic_vector ( 7 downto 0 ) [Port] |
T1_2 out std_logic_vector ( 7 downto 0 ) [Port] |
T2_1 out std_logic_vector ( 7 downto 0 ) [Port] |
T2_2 out std_logic_vector ( 7 downto 0 ) [Port] |
T3_1 out std_logic_vector ( 7 downto 0 ) [Port] |
T3_2 out std_logic_vector ( 7 downto 0 ) [Port] |
TX1N_OUT out std_logic_vector ( 1 downto 0 ) [Port] |
TX1P_OUT out std_logic_vector ( 1 downto 0 ) [Port] |
TX_READY_FLAG out std_logic [Port] |
TX_SYSTEM_RESET_IN in std_logic [Port] |
W1_1 out std_logic_vector ( 7 downto 0 ) [Port] |
W1_2 out std_logic_vector ( 7 downto 0 ) [Port] |
W2_1 out std_logic_vector ( 7 downto 0 ) [Port] |
W2_2 out std_logic_vector ( 7 downto 0 ) [Port] |
W3_1 out std_logic_vector ( 7 downto 0 ) [Port] |
W3_2 out std_logic_vector ( 7 downto 0 ) [Port] |
The documentation for this class was generated from the following file:
