auto_receiver.auto_receiver_arc Architecture Reference

receives packets from EMAC & decodes packets More...

Inheritance diagram for auto_receiver.auto_receiver_arc:

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Collaboration diagram for auto_receiver.auto_receiver_arc:

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List of all members.

Processes
latch_good	( clk )
	latch start of good packet
latch_bad	( clk )
	latch start of bad packet
FSM	( clk )
	FSM to step through data and decode it.
Types
states	( s_init , s_idle , s_wait , s_cnt , s_lenh , s_lenl , s_data , s_bad , s_rest , s_rdy , s_packet , s_datatype , s_arpreq )
Signals
currentstate	states := s_init
good_i	std_logic
bad_i	std_logic
busy_i	std_logic := ' 0 '
good_ff	std_logic := ' 0 '
bad_ff	std_logic := ' 0 '
lastpacketlen_i	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
sha_req	std_logic_vector ( 47 downto 0 ) := ( others = > ' 0 ' )
spa_req	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
Attributes
fsm_encoding	string
safe_implementation	string
fsm_encoding	" gray "
safe_implementation	" yes "

---

Detailed Description

receives packets from EMAC & decodes packets

Interface to Ethernet RX FIFO and FSM which steps through data byte-serial and decodes it

Definition at line 101 of file auto_receiver.vhd.

---

Member Function Documentation

[Process]

FSM

( clk )

FSM to step through data and decode it.

Definition at line 158 of file auto_receiver.vhd.

  FSM : process(clk)
    variable nextstate : states                       := s_init;
    variable cnt       : integer range 0 to 1500      := 0;
    variable byte      : std_logic_vector(1 downto 0) := "00";
    variable rxbuf     : std_logic_vector(7 downto 0);
  begin
    
    if (rising_edge(clk)) then
      
      nextstate := currentstate;
      ARP_vld   <= '0';

      if (rx_rderr = '0') then  -- in case of rderr we keep the current state
        
        case currentstate is
          
          when s_init =>
            
            cnt             := 0;
            rx_fifo_en      <= '0';
            ncm_rcv_data    <= (others => '0');
            ncm_rcv_en      <= '0';
            busy_i          <= '0';
            lastpacketlen_i <= (others => '0');
            ARP_vld         <= '0';
            SHA             <= (others => '0');
            SPA             <= (others => '0');
            sha_req         <= (others => '0');
            spa_req         <= (others => '0');

            nextstate := s_idle;
            
          when s_idle =>
            
            ncm_rcv_data <= (others => '0');
            data_type    <= (others => '0');
            ncm_rcv_en   <= '0';
            busy_i       <= '0';
            cnt          := 0;

            if (good_i = '1') then    -- good packet is in queue - read it out
              busy_i     <= '1';
              rx_fifo_en <= '1';        -- init rcv process
              nextstate  := s_wait;     -- wait one cycle to get data
            elsif (bad_i = '1') then    -- bad packet is in queue - reset queue
              busy_i    <= '1';
              nextstate := s_bad;
            else
              rx_fifo_en <= '0';
            end if;
            
          when s_wait =>
            
            cnt       := 0;
            nextstate := s_cnt;
            
          when s_cnt =>
            
            if (rx_valid = '0') then
              rx_fifo_en <= '0';
              nextstate  := s_rdy;
            else

              if cnt = 13 then
                if rx_fifo_data = x"06" then
                  nextstate := s_arpreq;
                  cnt       := 0;
                end if;
              elsif cnt = 41 then       --* step through Ethernet header (14
                nextstate := s_lenh;    --* bytes), IP header (20 bytes), UDP
              else                      --* header (8 bytes)
                nextstate := s_cnt;
              end if;
            end if;

--            if cnt = 25 then            --* check src ip
--              if rx_fifo_data /= rxsrcip(31 downto 24) then
--                nextstate := s_bad;
--              end if;
--            elsif cnt = 26 then
--              if rx_fifo_data /= rxsrcip(23 downto 16) then
--                nextstate := s_bad;
--              end if;
--            elsif cnt = 27 then
--              if rx_fifo_data /= rxsrcip(15 downto 8) then
--                nextstate := s_bad;
--              end if;
--            elsif cnt = 28 then
--              if rx_fifo_data /= rxsrcip(7 downto 0) then
--                nextstate := s_bad;
--              end if;
--            end if;

            if cnt = 30 then            --* check dest ip
              if rx_fifo_data /= rxdestip(31 downto 24) then
                nextstate := s_bad;
              end if;
            elsif cnt = 31 then
              if rx_fifo_data /= rxdestip(23 downto 16) then
                nextstate := s_bad;
              end if;
            elsif cnt = 32 then
              if rx_fifo_data /= rxdestip(15 downto 8) then
                nextstate := s_bad;
              end if;
            elsif cnt = 33 then
              if rx_fifo_data /= rxdestip(7 downto 0) then
                nextstate := s_bad;
              end if;
            end if;

--            if cnt = 35 then            --* check src port
--              if rx_fifo_data /= rxsrc_port(15 downto 8) then
--                nextstate := s_bad;
--              end if;
--            elsif cnt = 36 then
--              if rx_fifo_data /= rxsrc_port(7 downto 0) then
--                nextstate := s_bad;
--              end if;
--            end if;

            if cnt = 36 then            --* check dest port
              if rx_fifo_data /= rxdest_port(15 downto 8) then
                nextstate := s_bad;
              end if;
            elsif cnt = 37 then
              if rx_fifo_data /= rxdest_port(7 downto 0) then
                nextstate := s_bad;
              end if;
            end if;
            cnt := cnt + 1;

          when s_lenh =>                --* len of real data, expect length of
            cnt := 0;     --* packet in first 2 bytes of data block
            if (rx_valid = '0') then
              rx_fifo_en <= '0';
              nextstate  := s_rdy;
            else
              lastpacketlen_i(15 downto 8) <= rx_fifo_data;
              nextstate                    := s_lenl;
            end if;

          when s_lenl =>                -- len of real data

            if (rx_valid = '0') then
              rx_fifo_en <= '0';
              nextstate  := s_rdy;
            else
              lastpacketlen_i(7 downto 0) <= rx_fifo_data;
              cnt                         := 0;
              nextstate                   := s_packet;
            end if;
            
          when s_packet =>              --read the number of packet
            if (rx_valid = '0') then
              rx_fifo_en <= '0';
              nextstate  := s_rdy;
            else
              if cnt = 0 then
                packet(19 downto 12) <= rx_fifo_data;
              elsif cnt = 1 then
                packet(11 downto 4) <= rx_fifo_data;
              elsif cnt = 2 then
                packet(3 downto 0)     <= rx_fifo_data(7 downto 4);
                data_type(11 downto 8) <= rx_fifo_data(3 downto 0);
                nextstate              := s_datatype;
              end if;
              cnt := cnt + 1;
            end if;

          when s_datatype =>
            if (rx_valid = '0') then
              rx_fifo_en <= '0';
              nextstate  := s_rdy;
            else
              data_type(7 downto 0) <= rx_fifo_data;
              cnt                   := conv_integer(lastpacketlen_i);
              cnt                   := cnt;  -- -2
              nextstate             := s_data;
            end if;

          when s_data =>                -- read data and assemble dwords

            if (rx_valid = '0') then
              rx_fifo_en <= '0';
              ncm_rcv_en <= '0';
              nextstate  := s_rdy;

            else
              rx_fifo_en <= '1';

              rxbuf(7 downto 0) := rx_fifo_data;
                                        -- write to ncm fifo
              ncm_rcv_en        <= '1';
              ncm_rcv_data      <= rxbuf;

              cnt := cnt - 1;

              if (cnt = 0) then         -- all got
                nextstate := s_rest;
              end if;
            end if;

          when s_arpreq =>
            
            if (rx_valid = '0') then
              rx_fifo_en <= '0';
              ncm_rcv_en <= '0';
              nextstate  := s_rdy;

            else

              case cnt is
                when 1 =>
                  if rx_fifo_data /= x"00" then
                    nextstate := s_bad;
                  end if;
                when 2 =>
                  if rx_fifo_data /= x"01" then
                    nextstate := s_bad;
                  end if;
                when 3 =>
                  if rx_fifo_data /= x"08" then
                    nextstate := s_bad;
                  end if;
                when 4 =>
                  if rx_fifo_data /= x"00" then
                    nextstate := s_bad;
                  end if;
                when 5 =>
                  if rx_fifo_data /= x"06" then
                    nextstate := s_bad;
                  end if;
                when 6 =>
                  if rx_fifo_data /= x"04" then
                    nextstate := s_bad;
                  end if;
                when 7 =>
                  if rx_fifo_data /= x"00" then
                    nextstate := s_bad;
                  end if;
                when 8 =>
                  if rx_fifo_data /= x"01" then
                    nextstate := s_bad;
                  end if;
                when 9 =>
                  sha_req(47 downto 40) <= rx_fifo_data;
                when 10 =>
                  sha_req(39 downto 32) <= rx_fifo_data;
                when 11 =>
                  sha_req(31 downto 24) <= rx_fifo_data;
                when 12 =>
                  sha_req(23 downto 16) <= rx_fifo_data;
                when 13 =>
                  sha_req(15 downto 8) <= rx_fifo_data;
                when 14 =>
                  sha_req(7 downto 0) <= rx_fifo_data;
                when 15 =>
                  spa_req(31 downto 24) <= rx_fifo_data;
                when 16 =>
                  spa_req(23 downto 16) <= rx_fifo_data;
                when 17 =>
                  spa_req(15 downto 8) <= rx_fifo_data;
                when 18 =>
                  spa_req(7 downto 0) <= rx_fifo_data;
                when 19 =>
                  if rx_fifo_data /= x"00" then
                    nextstate := s_bad;
                  end if;
                when 20 =>
                  if rx_fifo_data /= x"00" then
                    nextstate := s_bad;
                  end if;
                when 21 =>
                  if rx_fifo_data /= x"00" then
                    nextstate := s_bad;
                  end if;
                when 22 =>
                  if rx_fifo_data /= x"00" then
                    nextstate := s_bad;
                  end if;
                when 23 =>
                  if rx_fifo_data /= x"00" then
                    nextstate := s_bad;
                  end if;
                when 24 =>
                  if rx_fifo_data /= x"00" then
                    nextstate := s_bad;
                  end if;
                when 25 =>
                  if rx_fifo_data /= rxdestip(31 downto 24) then
                    nextstate := s_bad;
                  end if;
                when 26 =>
                  if rx_fifo_data /= rxdestip(23 downto 16) then
                    nextstate := s_bad;
                  end if;
                when 27 =>
                  if rx_fifo_data /= rxdestip(15 downto 8) then
                    nextstate := s_bad;
                  end if;
                when 28 =>
                  if rx_fifo_data /= rxdestip(7 downto 0) then
                    nextstate := s_bad;
                  else
                    ARP_vld   <= '1';
                    SHA       <= sha_req;
                    SPA       <= spa_req;
                    nextstate := s_rest;
                  end if;
                when others => null;
              end case;

              cnt := cnt + 1;
            end if;


          when s_bad =>  -- bad packet in queue - read out rest until valid = 0

            rx_fifo_en <= '1';
            nextstate  := s_rest;

          when s_rest =>  -- read out rest of packet until valid = 0

            ncm_rcv_en   <= '0';
            ncm_rcv_data <= (others => '0');

            if (rx_valid = '0') then
              nextstate  := s_rdy;
              rx_fifo_en <= '0';
            else
              rx_fifo_en <= '1';
            end if;

          when s_rdy =>                 -- we made it

            cnt        := 0;
            rx_fifo_en <= '0';
            busy_i     <= '0';
            nextstate  := s_idle;

          when others =>

            nextstate := s_init;        -- to be safe
            
        end case;

      end if;  -- rderr

      currentstate <= nextstate;

    end if;

  end process;

[Process]

latch_bad

( clk )

latch start of bad packet

Definition at line 135 of file auto_receiver.vhd.

  latch_bad : process(clk)
  begin
    if clk'event and clk = '1' then
      if (en and rx_bad_packet) = '1' then
        bad_ff <= '1';
      elsif (bad_i and (not busy_i)) = '1' then
        bad_ff <= '0';
      end if;
    end if;
  end process latch_bad;

[Process]

latch_good

( clk )

latch start of good packet

Definition at line 124 of file auto_receiver.vhd.

  latch_good : process(clk)
  begin
    if clk'event and clk = '1' then
      if (en and rx_good_packet) = '1' then
        good_ff <= '1';
      elsif (good_i and (not busy_i)) = '1' then
        good_ff <= '0';
      end if;
    end if;
  end process latch_good;

---

The documentation for this class was generated from the following file:

• auto_receiver.vhd