ddr2_mem_rd_wr_addr_fifo_0.arc_rd_wr_addr_fifo Architecture Reference

FIFO for read/write address. More...

Inheritance diagram for ddr2_mem_rd_wr_addr_fifo_0.arc_rd_wr_addr_fifo:

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Collaboration diagram for ddr2_mem_rd_wr_addr_fifo_0.arc_rd_wr_addr_fifo:

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List of all members.

Processes
PROCESS_144	( clk0 )
PROCESS_145	( clk270 )
	A fix for FIFO16 according to answer record #22462.
PROCESS_146	( clk0 )
	3 Filp-flops logic is implemented at output to avoid the timimg errors
PROCESS_147	( clk90 )
	3 Filp-flops logic is implemented at output to avoid the timimg errors
PROCESS_148	( clk0 )
	3 Filp-flops logic is implemented at output to avoid the timimg errors
Components
FIFO16
	FIFO primitive.
Signals
fifo_input_write_addr	std_logic_vector ( 35 downto 0 )
fifo_output_write_addr	std_logic_vector ( 35 downto 0 )
compare_value_r	std_logic_vector ( 35 downto 0 )
app_af_addr_r	std_logic_vector ( 35 downto 0 )
fifo_input_addr_r	std_logic_vector ( 35 downto 0 )
af_en_r	std_logic
af_en_2r	std_logic
compare_result	std_logic
clk270	std_logic
af_al_full_0	std_logic
af_al_full_180	std_logic
af_al_full_90	std_logic
af_en_2r_270	std_logic
fifo_input_270	std_logic_vector ( 35 downto 0 )
Component Instantiations
Waf_fifo16	FIFO16
	Address FIFO.

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Detailed Description

FIFO for read/write address.

This module instantiates the block RAM based FIFO to store the user address and the command information.

Definition at line 74 of file ddr2_mem_rd_wr_addr_fifo_0.vhd.

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Member Function Documentation

[Process]

PROCESS_145

( clk270 )

A fix for FIFO16 according to answer record #22462.

Definition at line 151 of file ddr2_mem_rd_wr_addr_fifo_0.vhd.

  process(clk270)
  begin
    if (clk270'event and clk270 = '1') then
      af_en_2r_270   <= af_en_2r;
      fifo_input_270 <= fifo_input_addr_r;
    end if;
  end process;

[Process]

PROCESS_146

( clk0 )

3 Filp-flops logic is implemented at output to avoid the timimg errors

Definition at line 160 of file ddr2_mem_rd_wr_addr_fifo_0.vhd.

  process(clk0)
  begin
    if (clk0'event and clk0 = '0') then
      af_al_full_180 <= af_al_full_0;
    end if;
  end process;

[Process]

PROCESS_147

( clk90 )

3 Filp-flops logic is implemented at output to avoid the timimg errors

Definition at line 168 of file ddr2_mem_rd_wr_addr_fifo_0.vhd.

  process(clk90)
  begin
    if (clk90'event and clk90 = '1') then
      af_al_full_90 <= af_al_full_180;
    end if;
  end process;

[Process]

PROCESS_148

( clk0 )

3 Filp-flops logic is implemented at output to avoid the timimg errors

Definition at line 176 of file ddr2_mem_rd_wr_addr_fifo_0.vhd.

  process(clk0)
  begin
    if (clk0'event and clk0 = '1') then
      af_Almost_Full <= af_al_full_90;
    end if;
  end process;

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Member Data Documentation

FIFO16 [Component]

FIFO primitive.

Definition at line 77 of file ddr2_mem_rd_wr_addr_fifo_0.vhd.

Waf_fifo16 FIFO16 [Component Instantiation]

Address FIFO.

Definition at line 184 of file ddr2_mem_rd_wr_addr_fifo_0.vhd.

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The documentation for this class was generated from the following file:

• ddr2_mem_rd_wr_addr_fifo_0.vhd