Processes | |
cnt_rds | ( CLK ) |
Counter. | |
Signals | |
cnt | std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' ) |
done_i | std_logic := ' 0 ' |
Definition at line 51 of file cnt_ddr2_rd.vhd.
cnt_rds | ( CLK ) |
Counter.
Definition at line 61 of file cnt_ddr2_rd.vhd.
00061 cnt_rds : process(CLK) 00062 begin 00063 if CLK'event and CLK = '1' then 00064 if RESET = '1' then 00065 cnt <= (others => '0'); 00066 done_i <= '0'; 00067 else 00068 if cnt = "111111111111111111111111" then 00069 done_i <= '1'; 00070 cnt <= (others => '0'); 00071 else 00072 done_i <= '0'; 00073 end if; 00074 if (EN = '1' and done_i = '0') then 00075 cnt <= cnt + 1; 00076 else 00077 cnt <= cnt; 00078 end if; 00079 end if; 00080 end if; 00081 end process cnt_rds;