mem_interface_top_infrastructure Entity Reference
DCM for DDR specific clocks. More...
Inheritance diagram for mem_interface_top_infrastructure:
Collaboration diagram for mem_interface_top_infrastructure:
Architectures | |
| arch | Architecture |
| DCM for DDR specific clocks. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| SYS_CLK_N | in std_logic |
| 160 MHz clk n | |
| SYS_CLK_P | in std_logic |
| 160 MHz clk p | |
| CLK200_N | in std_logic |
| 200 MHz clk n | |
| CLK200_P | in std_logic |
| 200 MHz clk p | |
| SYS_RESET_IN | in std_logic |
| Reset. | |
| LOCK | in std_logic |
| Lock flag. | |
| CLK | out std_logic |
| 160 MHz | |
| CLK90 | out std_logic |
160 MHz  phase-shifted | |
| CLK200 | out std_logic |
| 200 MHz | |
| CLK50 | out std_logic |
| 50 MHz | |
| REFRESH_CLK | out std_logic |
| slow clock for RAM refreshes | |
| sys_rst | out std_logic |
| synchronized reset | |
| sys_rst90 | out std_logic |
| synchronized reset phase-shifted | |
| sys_rst_ref_clk_1 | out std_logic |
| reference clock for reset | |
Detailed Description
DCM for DDR specific clocks.Instantiates the DCM of the FPGA device. The system clock is given as the input and two clocks that are phase shifted by 90 degrees are taken out. It also give the reset signals in phase with the clocks.
Definition at line 53 of file mem_interface_top_infrastructure.vhd.
Member Data Documentation
CLK out std_logic [Port] |
CLK200 out std_logic [Port] |
CLK200_N in std_logic [Port] |
CLK200_P in std_logic [Port] |
CLK50 out std_logic [Port] |
CLK90 out std_logic [Port] |
ieee library [Library] |
LOCK in std_logic [Port] |
REFRESH_CLK out std_logic [Port] |
std_logic_1164 package [Package] |
SYS_CLK_N in std_logic [Port] |
SYS_CLK_P in std_logic [Port] |
SYS_RESET_IN in std_logic [Port] |
sys_rst out std_logic [Port] |
sys_rst90 out std_logic [Port] |
synchronized reset phase-shifted
Definition at line 68 of file mem_interface_top_infrastructure.vhd.
sys_rst_ref_clk_1 out std_logic [Port] |
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
