extend_test.extend_test_arc Architecture Reference
Extending a pulse. More...
Inheritance diagram for extend_test.extend_test_arc:
Collaboration diagram for extend_test.extend_test_arc:
Processes | |
| extend | ( CLK ) |
| Pulse extender. | |
Signals | |
| cn | std_logic_vector ( 5 downto 0 ) := " 000000 " |
| enab | std_logic := ' 0 ' |
Detailed Description
Extending a pulse.This Entity extends a pulse by up to 63 clock periods.
Definition at line 53 of file extend_test.vhd.
Member Function Documentation
| extend | ( CLK ) |
Pulse extender.
Definition at line 63 of file extend_test.vhd.
00063 extend : process(CLK) 00064 begin 00065 if(CLK'event and CLK = '1') then 00066 if RES = '1' then 00067 cn <= (others => '0'); 00068 ENDM <= '0'; 00069 else 00070 ENDM <= '0'; 00071 if enab = '1' then 00072 if cn = LEN then 00073 cn <= (others => '0'); 00074 enab <= '0'; 00075 ENDM <= '1'; 00076 else 00077 cn <= cn + 1; 00078 end if; 00079 else 00080 cn <= cn; 00081 end if; 00082 if A = '1' then 00083 enab <= '1'; 00084 end if; 00085 end if; 00086 end if; 00087 end process extend;
The documentation for this class was generated from the following file:
