comparator4 Entity Reference
4-Input greatest value selector
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List of all members.
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Architectures |
| comparator4_arc | Architecture |
| | 4-Input greatest value selector More...
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Libraries |
| ieee | |
| | standard IEEE library
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| unisim | |
| | Library with Xilinx primitives.
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Packages |
| std_logic_1164 | |
| | std_logic definitions, see file
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| std_logic_arith | |
| | arithmetic operations on std_logic datatypes, see file
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| std_logic_unsigned | |
| | unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
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| vcomponents | |
| | Header with Xilinx primitives.
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Ports |
| CLK | in |
| | Clock.
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| SA | in |
| | Status Bit Input A.
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| SB | in |
| | Status Bit Input B.
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| SC | in |
| | Status Bit Input C.
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| SD | in |
| | Status Bit Input D.
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| A | in ( 5 downto 0 ) |
| | Input A.
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| B | in ( 5 downto 0 ) |
| | Input B.
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| C | in ( 5 downto 0 ) |
| | Input C.
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| D | in ( 5 downto 0 ) |
| | Input D.
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| SY | out |
| | Output status flag.
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| Y | out ( 5 downto 0 ) |
| | Output = greatest Input value.
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Detailed Description
4-Input greatest value selector
Pipelined comparator module to determine the greatest value of four 6-bit input values with an additional enable bit per input.
Definition at line 40 of file comparator4.vhd.
Member Data Documentation
A in ( 5 downto 0 ) [Port] |
B in ( 5 downto 0 ) [Port] |
C in ( 5 downto 0 ) [Port] |
D in ( 5 downto 0 ) [Port] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 30 of file comparator4.vhd.
Y out ( 5 downto 0 ) [Port] |
The documentation for this class was generated from the following file:
