ddr2_mem Entity Reference
Structure of DDR2 Controller. More...
Inheritance diagram for ddr2_mem:
Collaboration diagram for ddr2_mem:
Architectures | |
| arc_ddr2_mem | Architecture |
| Structure of DDR2 Controller. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| cntrl0_DDR2_DQ | inout std_logic_vector ( 63 downto 0 ) |
| cntrl0_DDR2_A | out std_logic_vector ( 13 downto 0 ) |
| cntrl0_DDR2_BA | out std_logic_vector ( 1 downto 0 ) |
| cntrl0_DDR2_RAS_N | out std_logic |
| cntrl0_DDR2_CAS_N | out std_logic |
| cntrl0_DDR2_WE_N | out std_logic |
| cntrl0_DDR2_RESET_N | out std_logic |
| cntrl0_DDR2_CS_N | out std_logic |
| cntrl0_DDR2_ODT | out std_logic |
| cntrl0_DDR2_CKE | out std_logic |
| cntrl0_DDR2_DM | out std_logic_vector ( 7 downto 0 ) |
| SYS_CLK_P | in std_logic |
| SYS_CLK_N | in std_logic |
| CLK200_P | in std_logic |
| CLK200_N | in std_logic |
| SYS_RESET_IN | in std_logic |
| cntrl0_CLK_TB | out std_logic |
| cntrl0_RESET_TB | out std_logic |
| cntrl0_WDF_ALMOST_FULL | out std_logic |
| cntrl0_AF_ALMOST_FULL | out std_logic |
| cntrl0_READ_DATA_VALID | out std_logic |
| cntrl0_APP_WDF_WREN | in std_logic |
| cntrl0_APP_AF_WREN | in std_logic |
| cntrl0_BURST_LENGTH | out std_logic_vector ( 2 downto 0 ) |
| cntrl0_APP_AF_ADDR | in std_logic_vector ( 35 downto 0 ) |
| cntrl0_READ_DATA_FIFO_OUT | out std_logic_vector ( 127 downto 0 ) |
| cntrl0_APP_WDF_DATA | in std_logic_vector ( 127 downto 0 ) |
| cntrl0_APP_MASK_DATA | in std_logic_vector ( 15 downto 0 ) |
| cntrl0_DDR2_DQS | inout std_logic_vector ( 7 downto 0 ) |
| cntrl0_DDR2_DQS_N | inout std_logic_vector ( 7 downto 0 ) |
| cntrl0_DDR2_CK | out std_logic |
| cntrl0_DDR2_CK_N | out std_logic |
| LOCK_IN | in std_logic |
Detailed Description
Structure of DDR2 Controller.It is the top most module which interfaces with the system and the memory.
Definition at line 59 of file ddr2_mem.vhd.
Member Data Documentation
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 48 of file ddr2_mem.vhd.
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 46 of file ddr2_mem.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
