ddr2_mem_v4_dqs_iob.arc_v4_dqs_iob Architecture Reference

DDR2 data strobe IOBs. More...

Inheritance diagram for ddr2_mem_v4_dqs_iob.arc_v4_dqs_iob:

Inheritance graph
[legend]
Collaboration diagram for ddr2_mem_v4_dqs_iob.arc_v4_dqs_iob:

Collaboration graph
[legend]

List of all members.


Processes

PROCESS_163  ( clk180 )
 FF enable.
PROCESS_164  ( clk180 )
 FF enable.

Components

FD 
 D-FF primitive.
IDELAY 
 iDelay primitive
IDDR 
 DDR input buffer.
ODDR 
 DDR output buffer.
IOBUFDS 
 bidirectional IO-Buffer

Signals

dqs_in  std_logic
dqs_out  std_logic
dqs_out_l  std_logic
dqs_delayed  std_logic
ctrl_dqs_en_r1  std_logic
vcc  std_logic
gnd  std_logic
clk180  std_logic
data1  std_logic
data2  std_logic
DQS_UNUSED  std_logic

Component Instantiations

idelay_dqs IDELAY
 iDelay instance
iddr_dqs IDDR
 DDR input buffer.
oddr_dqs ODDR
 DDR output buffer.
oddr_dqs_l ODDR
 DDR output buffer.
tri_state_dqs FD
 FF.
iobuf_dqs IOBUFDS
 IO-Buffer.


Detailed Description

DDR2 data strobe IOBs.

This module places the data stobes in the IOBs.

Definition at line 74 of file ddr2_mem_v4_dqs_iob.vhd.


Member Function Documentation

[Process]
PROCESS_163 ( clk180 )

FF enable.

Definition at line 167 of file ddr2_mem_v4_dqs_iob.vhd.

00167   process(clk180)
00168   begin
00169     if clk180'event and clk180 = '1' then
00170       if (CTRL_DQS_RST = '1') then
00171         data1 <= '0';
00172       else
00173         data1 <= '1';
00174       end if;
00175     end if;
00176   end process;

[Process]
PROCESS_164 ( clk180 )

FF enable.

Definition at line 179 of file ddr2_mem_v4_dqs_iob.vhd.

00179   process(clk180)
00180   begin
00181     if clk180'event and clk180 = '1' then
00182       if (CTRL_DQS_RST = '1') then
00183         data2 <= '1';
00184       else
00185         data2 <= '0';
00186       end if;
00187     end if;
00188   end process;


Member Data Documentation

FD [Component]

D-FF primitive.

Definition at line 77 of file ddr2_mem_v4_dqs_iob.vhd.

IDDR [Component]

DDR input buffer.

Definition at line 102 of file ddr2_mem_v4_dqs_iob.vhd.

iddr_dqs IDDR [Component Instantiation]

DDR input buffer.

Definition at line 207 of file ddr2_mem_v4_dqs_iob.vhd.

IDELAY [Component]

iDelay primitive

Definition at line 86 of file ddr2_mem_v4_dqs_iob.vhd.

idelay_dqs IDELAY [Component Instantiation]

iDelay instance

Definition at line 191 of file ddr2_mem_v4_dqs_iob.vhd.

iobuf_dqs IOBUFDS [Component Instantiation]

IO-Buffer.

Definition at line 264 of file ddr2_mem_v4_dqs_iob.vhd.

IOBUFDS [Component]

bidirectional IO-Buffer

Definition at line 136 of file ddr2_mem_v4_dqs_iob.vhd.

ODDR [Component]

DDR output buffer.

Definition at line 119 of file ddr2_mem_v4_dqs_iob.vhd.

oddr_dqs ODDR [Component Instantiation]

DDR output buffer.

Definition at line 223 of file ddr2_mem_v4_dqs_iob.vhd.

oddr_dqs_l ODDR [Component Instantiation]

DDR output buffer.

Definition at line 240 of file ddr2_mem_v4_dqs_iob.vhd.

tri_state_dqs FD [Component Instantiation]

FF.

Definition at line 256 of file ddr2_mem_v4_dqs_iob.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 00:50:54 2008 for BCM-AAA by doxygen 1.5.7.1-20081012