ddr_chksum_cal Entity Reference

Running UDP checksum calculation DDR. More...

Inheritance diagram for ddr_chksum_cal:

Inheritance graph
[legend]
Collaboration diagram for ddr_chksum_cal:

Collaboration graph
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List of all members.


Architectures

ddr_dsp_chksum_cal_arc Architecture
 Running UDP checksum calculation DDR. More...

Libraries

ieee 
 standard IEEE library
unisim 
 Library with Xilinx primitives.

Packages

std_logic_1164 
 std_logic definitions, see file
vcomponents 
 Header with Xilinx primitives.

Ports

CLK  in std_logic
 Clock.
RESET  in std_logic
 Reset.
EN  in std_logic
 Enable.
DATA_IN  in std_logic_vector ( 63 downto 0 )
 Data input.
WRITE_DONE  in std_logic
 All data read for this packet.
READ_DATA  in std_logic
 Get last computed value.
CAL_COMPL  out std_logic
 Computation done, after asserting Write_done wait until this is high to set EN again.
DATA_OUT  out std_logic_vector ( 15 downto 0 )
 last computed value


Detailed Description

Running UDP checksum calculation DDR.

This entity does a running checksum calculation according to the UDP protocol specification.

Definition at line 36 of file ddr_chksum_cal.vhd.


Member Data Documentation

CAL_COMPL out std_logic [Port]

Computation done, after asserting Write_done wait until this is high to set EN again.

Definition at line 45 of file ddr_chksum_cal.vhd.

CLK in std_logic [Port]

Clock.

Definition at line 39 of file ddr_chksum_cal.vhd.

DATA_IN in std_logic_vector ( 63 downto 0 ) [Port]

Data input.

Definition at line 42 of file ddr_chksum_cal.vhd.

DATA_OUT out std_logic_vector ( 15 downto 0 ) [Port]

last computed value

Definition at line 46 of file ddr_chksum_cal.vhd.

EN in std_logic [Port]

Enable.

Definition at line 41 of file ddr_chksum_cal.vhd.

ieee library [Library]

standard IEEE library

Reimplemented in main_components.

Definition at line 25 of file ddr_chksum_cal.vhd.

READ_DATA in std_logic [Port]

Get last computed value.

Definition at line 44 of file ddr_chksum_cal.vhd.

RESET in std_logic [Port]

Reset.

Definition at line 40 of file ddr_chksum_cal.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Reimplemented in main_components.

Definition at line 27 of file ddr_chksum_cal.vhd.

unisim library [Library]

Library with Xilinx primitives.

Definition at line 29 of file ddr_chksum_cal.vhd.

vcomponents package [Package]

Header with Xilinx primitives.

Definition at line 31 of file ddr_chksum_cal.vhd.

WRITE_DONE in std_logic [Port]

All data read for this packet.

Definition at line 43 of file ddr_chksum_cal.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 00:51:01 2008 for BCM-AAA by doxygen 1.5.7.1-20081012