Architectures | |
ddr_dsp_chksum_cal_arc | Architecture |
Running UDP checksum calculation DDR. More... | |
Libraries | |
ieee | |
standard IEEE library | |
unisim | |
Library with Xilinx primitives. | |
Packages | |
std_logic_1164 | |
std_logic definitions, see file | |
vcomponents | |
Header with Xilinx primitives. | |
Ports | |
CLK | in std_logic |
Clock. | |
RESET | in std_logic |
Reset. | |
EN | in std_logic |
Enable. | |
DATA_IN | in std_logic_vector ( 63 downto 0 ) |
Data input. | |
WRITE_DONE | in std_logic |
All data read for this packet. | |
READ_DATA | in std_logic |
Get last computed value. | |
CAL_COMPL | out std_logic |
Computation done, after asserting Write_done wait until this is high to set EN again. | |
DATA_OUT | out std_logic_vector ( 15 downto 0 ) |
last computed value |
This entity does a running checksum calculation according to the UDP protocol specification.
Definition at line 36 of file ddr_chksum_cal.vhd.
CAL_COMPL out std_logic [Port] |
Computation done, after asserting Write_done wait until this is high to set EN again.
Definition at line 45 of file ddr_chksum_cal.vhd.
CLK in std_logic [Port] |
DATA_IN in std_logic_vector ( 63 downto 0 ) [Port] |
DATA_OUT out std_logic_vector ( 15 downto 0 ) [Port] |
EN in std_logic [Port] |
ieee library [Library] |
standard IEEE library
Reimplemented in main_components.
Definition at line 25 of file ddr_chksum_cal.vhd.
READ_DATA in std_logic [Port] |
RESET in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 27 of file ddr_chksum_cal.vhd.
unisim library [Library] |
vcomponents package [Package] |
WRITE_DONE in std_logic [Port] |