ddr2_mem_ddr2_controller_0.arc_controller Architecture Reference
Main RAM controller module. More...
Inheritance diagram for ddr2_mem_ddr2_controller_0.arc_controller:
Collaboration diagram for ddr2_mem_ddr2_controller_0.arc_controller:
Processes | |
| PROCESS_40 | ( clk0 ) |
| PROCESS_41 | ( clk0 ) |
| PROCESS_42 | ( command_address , ctrl_init_done , af_empty ) |
| commands | |
| PROCESS_43 | ( clk0 ) |
| register address outputs | |
| PROCESS_44 | ( clk0 ) |
| register address outputs | |
| PROCESS_45 | ( clk0 ) |
| PROCESS_46 | ( clk0 ) |
| PROCESS_47 | ( clk0 ) |
| to initialize memory | |
| PROCESS_48 | ( clk0 ) |
| mrd count | |
| PROCESS_49 | ( clk0 ) |
| rp count | |
| PROCESS_50 | ( clk0 ) |
| rfc count | |
| PROCESS_51 | ( clk0 ) |
| rcd count - 20ns | |
| PROCESS_52 | ( clk0 ) |
| ras count - active to precharge | |
| PROCESS_53 | ( clk0 ) |
| PROCESS_54 | ( clk0 ) |
| PROCESS_55 | ( clk0 ) |
| PROCESS_56 | ( clk0 ) |
| read to write counter | |
| PROCESS_57 | ( refresh_clk ) |
| auto refresh interval counter in refresh_clk domain | |
| PROCESS_58 | ( refi_count , done_200us ) |
| end of 200us flag | |
| PROCESS_59 | ( refresh_clk ) |
| PROCESS_60 | ( clk0 ) |
| refresh detect in 266 MHz clock | |
| PROCESS_61 | ( clk0 ) |
| PROCESS_62 | ( clk0 ) |
| PROCESS_63 | ( clk0 ) |
| 200 clocks counter done flag | |
| PROCESS_64 | ( clk0 ) |
| init_done flag | |
| PROCESS_65 | ( BURST_LENGTH_VALUE ) |
| register burst_length | |
| PROCESS_66 | ( clk0 ) |
| init FSM | |
| PROCESS_67 | ( clk0 ) |
| init FSM | |
| PROCESS_68 | ( clk0 ) |
| determine number of chips for deep memories | |
| PROCESS_69 | ( clk0 ) |
| auto refresh count | |
| PROCESS_70 | ( clk0 ) |
| Precharge fix for deep memory. | |
| PROCESS_71 | ( clk0 ) |
| write burst count | |
| PROCESS_72 | ( clk0 ) |
| read burst count for state machine | |
| PROCESS_73 | ( clk0 ) |
| count to generate write enable to the data path | |
| PROCESS_74 | ( ctrl_WrEn_cnt ) |
| write enable to data path | |
| PROCESS_75 | ( clk0 ) |
| write enable to data path | |
| PROCESS_76 | ( state , init_state ) |
| reset DQS | |
| PROCESS_77 | ( clk0 ) |
| DQS reset to data path. | |
| PROCESS_78 | ( state , init_state , wrburst_cnt ) |
| enable DQS | |
| PROCESS_79 | ( clk0 ) |
| DQS enable to data path. | |
| PROCESS_80 | ( clk0 ) |
| cas count | |
| PROCESS_81 | ( clk0 ) |
| dummy_read enable | |
| PROCESS_82 | ( clk0 ) |
| ctrl_Dummyread_Start signal generation to the data path module | |
| PROCESS_83 | ( clk0 ) |
| register ctrl_Dummyread_Start signal | |
| PROCESS_84 | ( clk0 ) |
| PROCESS_85 | ( clk0 ) |
| cas check | |
| PROCESS_86 | ( clk0 ) |
| read burst count | |
| PROCESS_87 | ( rdburst_cnt ) |
| read enable to data path | |
| PROCESS_88 | ( clk0 ) |
| read enable to data path | |
| PROCESS_89 | ( clk0 ) |
| read enable to data path | |
| PROCESS_90 | ( clk0 ) |
| write address FIFO read enable signals | |
| PROCESS_91 | ( clk0 ) |
| write data fifo read enable | |
| PROCESS_92 | ( burst_cnt , wdf_rden_r , wdf_rden_r2 , wdf_rden_r3 , wdf_rden_r4 ) |
| Read enable to the data fifo. | |
| PROCESS_93 | ( clk0 ) |
| Read enable to the data fifo. | |
| PROCESS_94 | ( clk0 ) |
| hold init for a while | |
| PROCESS_95 | ( clk0 ) |
| initialize FSM | |
| PROCESS_96 | ( clk0 ) |
| FSM state transitions. | |
| PROCESS_97 | ( clk0 ) |
| dummy write flag FF | |
| PROCESS_98 | ( clk0 ) |
| init dummy write state | |
| PROCESS_99 | ( RD , RD_r , WR , WR_r , LMR_r , PRE_r , ACT_r , REF_r , auto_ref , chip_cnt , auto_cnt , conflict_detect , conflict_detect_r , conflict_resolved_r , count_200cycle_done_r , idle_cnt , init_count , init_memory , mrd_count , LMR_PRE_REF_ACT_cmd_r , phy_Dly_Slct_Done , ras_count , rcd_count , rd_to_wr_count , read_burst_cnt , rfc_count , rp_count , rtp_count , init_state , wr_to_rd_count , wrburst_cnt , wtp_count , done_200us , cs_width0 , dummy_write_flag_r , COMP_DONE_r , count6 ) |
| init state machine | |
| PROCESS_100 | ( RD , RD_r , WR , WR_r , LMR_r , PRE_r , ACT_r , REF_r , auto_ref , chip_cnt , auto_cnt , conflict_detect , conflict_detect_r , conflict_resolved_r , count_200cycle_done_r , idle_cnt , init_count , init_memory , mrd_count , LMR_PRE_REF_ACT_cmd_r , phy_Dly_Slct_Done , ras_count , rcd_count , rd_to_wr_count , read_burst_cnt , rfc_count , rp_count , rtp_count , pre_cnt , state , wr_to_rd_count , wrburst_cnt , wtp_count , done_200us , cs_width1 , dummy_write_flag_r , COMP_DONE_r , init_done , af_empty_r ) |
| main control state machine | |
| PROCESS_101 | ( clk0 ) |
| register command outputs | |
| PROCESS_102 | ( clk0 ) |
| commands to the memory | |
| PROCESS_103 | ( clk0 ) |
| commands to the memory | |
| PROCESS_104 | ( clk0 ) |
| commands to the memory | |
| PROCESS_105 | ( clk0 ) |
| register commands to the memory | |
| PROCESS_106 | ( clk0 ) |
| register commands to the memory | |
| PROCESS_107 | ( clk0 ) |
| build address | |
| PROCESS_108 | ( clk0 ) |
| chip enable generation logic | |
| PROCESS_109 | ( clk0 ) |
| address during init | |
| PROCESS_110 | ( clk0 ) |
| address assembly | |
| PROCESS_111 | ( clk0 ) |
| register address to RAM | |
| PROCESS_112 | ( clk0 ) |
| bank address during init | |
| PROCESS_113 | ( clk0 ) |
| register bank address to RAM | |
| PROCESS_114 | ( clk0 ) |
| MUX chip select. | |
| PROCESS_115 | ( clk0 ) |
| register chip select to RAM | |
| PROCESS_116 | ( clk0 ) |
| ??? | |
| PROCESS_117 | ( clk0 ) |
| register clock enable to RAM | |
| PROCESS_118 | ( clk0 ) |
| odt | |
| PROCESS_119 | ( clk0 ) |
| odt count | |
| PROCESS_120 | ( rst , odt_en_cnt , odt_cnt ) |
| odt_en logic is made combinational to add a flop to the ctrl_odt logic | |
| PROCESS_121 | ( clk0 ) |
| added for deep designs | |
Constants | |
| INIT_IDLE | std_logic_vector ( 4 downto 0 ) := " 00000 " |
| INIT_LOAD_MODE | std_logic_vector ( 4 downto 0 ) := " 00001 " |
| INIT_MODE_REGISTER_WAIT | std_logic_vector ( 4 downto 0 ) := " 00010 " |
| INIT_PRECHARGE | std_logic_vector ( 4 downto 0 ) := " 00011 " |
| INIT_PRECHARGE_WAIT | std_logic_vector ( 4 downto 0 ) := " 00100 " |
| INIT_AUTO_REFRESH | std_logic_vector ( 4 downto 0 ) := " 00101 " |
| INIT_AUTO_REFRESH_WAIT | std_logic_vector ( 4 downto 0 ) := " 00110 " |
| INIT_COUNT_200 | std_logic_vector ( 4 downto 0 ) := " 00111 " |
| INIT_COUNT_200_WAIT | std_logic_vector ( 4 downto 0 ) := " 01000 " |
| INIT_DUMMY_READ_CYCLES | std_logic_vector ( 4 downto 0 ) := " 01001 " |
| INIT_DUMMY_ACTIVE | std_logic_vector ( 4 downto 0 ) := " 01010 " |
| INIT_DUMMY_ACTIVE_WAIT | std_logic_vector ( 4 downto 0 ) := " 01011 " |
| INIT_DUMMY_READ | std_logic_vector ( 4 downto 0 ) := " 01100 " |
| INIT_DUMMY_READ_WAIT | std_logic_vector ( 4 downto 0 ) := " 01101 " |
| INIT_DUMMY_FIRST_READ | std_logic_vector ( 4 downto 0 ) := " 01110 " |
| INIT_DEEP_MEMORY_ST | std_logic_vector ( 4 downto 0 ) := " 01111 " |
| INIT_ACTIVE | std_logic_vector ( 4 downto 0 ) := " 10000 " |
| INIT_ACTIVE_WAIT | std_logic_vector ( 4 downto 0 ) := " 10001 " |
| INIT_PATTERN_WRITE | std_logic_vector ( 4 downto 0 ) := " 10010 " |
| INIT_PATTERN_WRITE_READ | std_logic_vector ( 4 downto 0 ) := " 10011 " |
| INIT_PATTERN_READ | std_logic_vector ( 4 downto 0 ) := " 10100 " |
| INIT_PATTERN_READ_WAIT | std_logic_vector ( 4 downto 0 ) := " 10101 " |
| IDLE | std_logic_vector ( 4 downto 0 ) := " 00000 " |
| LOAD_MODE | std_logic_vector ( 4 downto 0 ) := " 00001 " |
| MODE_REGISTER_WAIT | std_logic_vector ( 4 downto 0 ) := " 00010 " |
| PRECHARGE | std_logic_vector ( 4 downto 0 ) := " 00011 " |
| PRECHARGE_WAIT | std_logic_vector ( 4 downto 0 ) := " 00100 " |
| AUTO_REFRESH | std_logic_vector ( 4 downto 0 ) := " 00101 " |
| AUTO_REFRESH_WAIT | std_logic_vector ( 4 downto 0 ) := " 00110 " |
| ACTIVE | std_logic_vector ( 4 downto 0 ) := " 00111 " |
| ACTIVE_WAIT | std_logic_vector ( 4 downto 0 ) := " 01000 " |
| FIRST_READ | std_logic_vector ( 4 downto 0 ) := " 01001 " |
| BURST_READ | std_logic_vector ( 4 downto 0 ) := " 01010 " |
| READ_WAIT | std_logic_vector ( 4 downto 0 ) := " 01011 " |
| FIRST_WRITE | std_logic_vector ( 4 downto 0 ) := " 01100 " |
| BURST_WRITE | std_logic_vector ( 4 downto 0 ) := " 01101 " |
| WRITE_WAIT | std_logic_vector ( 4 downto 0 ) := " 01110 " |
| WRITE_READ | std_logic_vector ( 4 downto 0 ) := " 01111 " |
| READ_WRITE | std_logic_vector ( 4 downto 0 ) := " 10000 " |
| cntnext | std_logic_vector ( 5 downto 0 ) := " 101000 " |
Signals | |
| init_count | std_logic_vector ( 3 downto 0 ) |
| init_count_cp | std_logic_vector ( 3 downto 0 ) |
| init_memory | std_logic |
| count_200_cycle | std_logic_vector ( 7 downto 0 ) |
| ref_flag | std_logic |
| ref_flag_266 | std_logic |
| ref_flag_266_r | std_logic |
| auto_ref | std_logic |
| next_state | std_logic_vector ( 4 downto 0 ) |
| state | std_logic_vector ( 4 downto 0 ) |
| state_r2 | std_logic_vector ( 4 downto 0 ) |
| state_r3 | std_logic_vector ( 4 downto 0 ) |
| init_next_state | std_logic_vector ( 4 downto 0 ) |
| init_state | std_logic_vector ( 4 downto 0 ) |
| init_state_r2 | std_logic_vector ( 4 downto 0 ) |
| row_addr_r | std_logic_vector ( ( row_address-1 ) downto 0 ) |
| ddr2_address_init_r | std_logic_vector ( ( row_address-1 ) downto 0 ) |
| ddr2_address_r1 | std_logic_vector ( ( row_address-1 ) downto 0 ) |
| ddr2_address_r2 | std_logic_vector ( ( row_address-1 ) downto 0 ) |
| ddr2_ba_r1 | std_logic_vector ( ( bank_address-1 ) downto 0 ) |
| ddr2_ba_r2 | std_logic_vector ( ( bank_address-1 ) downto 0 ) |
| mrd_count | std_logic |
| rp_count | std_logic_vector ( 2 downto 0 ) |
| rfc_count | std_logic_vector ( 5 downto 0 ) |
| rcd_count | std_logic_vector ( 2 downto 0 ) |
| ras_count | std_logic_vector ( 3 downto 0 ) |
| wr_to_rd_count | std_logic_vector ( 3 downto 0 ) |
| rd_to_wr_count | std_logic_vector ( 3 downto 0 ) |
| rtp_count | std_logic_vector ( 3 downto 0 ) |
| wtp_count | std_logic_vector ( 3 downto 0 ) |
| refi_count | std_logic_vector ( 7 downto 0 ) |
| cas_count | std_logic_vector ( 2 downto 0 ) |
| cas_check_count | std_logic_vector ( 3 downto 0 ) |
| wrburst_cnt | std_logic_vector ( 2 downto 0 ) |
| read_burst_cnt | std_logic_vector ( 2 downto 0 ) |
| ctrl_WrEn_cnt | std_logic_vector ( 2 downto 0 ) |
| rdburst_cnt | std_logic_vector ( 3 downto 0 ) |
| af_addr_r | std_logic_vector ( 35 downto 0 ) |
| af_addr_r1 | std_logic_vector ( 35 downto 0 ) |
| wdf_rden_r | std_logic |
| wdf_rden_r2 | std_logic |
| wdf_rden_r3 | std_logic |
| wdf_rden_r4 | std_logic |
| ctrl_Wdf_RdEn_int | std_logic |
| af_rden | std_logic |
| ddr2_ras_r2 | std_logic |
| ddr2_cas_r2 | std_logic |
| ddr2_we_r2 | std_logic |
| ddr2_ras_r | std_logic |
| ddr2_cas_r | std_logic |
| ddr2_we_r | std_logic |
| ddr2_ras_r3 | std_logic |
| ddr2_cas_r3 | std_logic |
| ddr2_we_r3 | std_logic |
| idle_cnt | std_logic_vector ( 3 downto 0 ) |
| ctrl_Dummyread_Start_r1 | std_logic := ' 0 ' |
| ctrl_Dummyread_Start_r2 | std_logic := ' 0 ' |
| ctrl_Dummyread_Start_r3 | std_logic := ' 0 ' |
| ctrl_Dummyread_Start_r4 | std_logic := ' 0 ' |
| conflict_resolved_r | std_logic |
| dqs_reset | std_logic |
| dqs_reset_r1 | std_logic |
| dqs_reset_r2 | std_logic |
| dqs_reset_r3 | std_logic |
| dqs_reset_r4 | std_logic |
| dqs_reset_r5 | std_logic |
| dqs_reset_r6 | std_logic |
| dqs_en | std_logic |
| dqs_en_r1 | std_logic |
| dqs_en_r2 | std_logic |
| dqs_en_r3 | std_logic |
| dqs_en_r4 | std_logic |
| dqs_en_r5 | std_logic |
| dqs_en_r6 | std_logic |
| ctrl_wdf_read_en | std_logic |
| ctrl_wdf_read_en_r1 | std_logic |
| ctrl_wdf_read_en_r2 | std_logic |
| ctrl_wdf_read_en_r3 | std_logic |
| ctrl_wdf_read_en_r4 | std_logic |
| ctrl_wdf_read_en_r5 | std_logic |
| ctrl_wdf_read_en_r6 | std_logic |
| ddr2_cs_r1 | std_logic |
| ddr2_cs_r | std_logic |
| ddr2_cke_r | std_logic |
| chip_cnt | std_logic_vector ( 1 downto 0 ) |
| auto_cnt | std_logic_vector ( 2 downto 0 ) |
| pre_cnt | std_logic_vector ( 2 downto 0 ) |
| dummy_read_en | std_logic |
| ctrl_init_done | std_logic |
| count_200cycle_done_r | std_logic |
| init_done | std_logic |
| burst_cnt | std_logic_vector ( 2 downto 0 ) |
| ctrl_write_en | std_logic |
| ctrl_write_en_r1 | std_logic |
| ctrl_write_en_r2 | std_logic |
| ctrl_write_en_r3 | std_logic |
| ctrl_write_en_r4 | std_logic |
| ctrl_write_en_r5 | std_logic |
| ctrl_write_en_r6 | std_logic |
| ctrl_read_en | std_logic |
| ctrl_read_en_r | std_logic |
| ctrl_read_en_r1 | std_logic |
| ctrl_read_en_r2 | std_logic |
| ctrl_read_en_r3 | std_logic |
| odt_cnt | std_logic_vector ( 3 downto 0 ) |
| odt_en_cnt | std_logic_vector ( 3 downto 0 ) |
| odt_en | std_logic |
| conflict_detect | std_logic |
| conflict_detect_r | std_logic |
| load_mode_reg | std_logic_vector ( ( row_address-1 ) downto 0 ) |
| ext_mode_reg | std_logic_vector ( ( row_address-1 ) downto 0 ) |
| CAS_LATENCY_VALUE | std_logic_vector ( 2 downto 0 ) |
| BURST_LENGTH_VALUE | std_logic_vector ( 2 downto 0 ) |
| ADDITIVE_LATENCY_VALUE | std_logic_vector ( 2 downto 0 ) |
| ODT_ENABLE | std_logic |
| REGISTERED_VALUE | std_logic |
| ECC_VALUE | std_logic |
| WR | std_logic |
| RD | std_logic |
| LMR | std_logic |
| PRE | std_logic |
| REF | std_logic |
| ACT | std_logic |
| WR_r | std_logic |
| RD_r | std_logic |
| LMR_r | std_logic |
| PRE_r | std_logic |
| REF_r | std_logic |
| ACT_r | std_logic |
| af_empty_r | std_logic |
| LMR_PRE_REF_ACT_cmd_r | std_logic |
| cke_200us_cnt | std_logic_vector ( 4 downto 0 ) |
| done_200us | std_logic |
| dummy_write_state_r | std_logic |
| dummy_write_state | std_logic |
| ctrl_dummy_write | std_logic |
| dummy_write_flag_r | std_logic |
| command_address | std_logic_vector ( 2 downto 0 ) |
| ctrl_odt | std_logic |
| cs_width0 | std_logic_vector ( 1 downto 0 ) |
| cs_width1 | std_logic_vector ( 2 downto 0 ) |
| s5_h | std_logic_vector ( 3 downto 0 ) |
| s3_h | std_logic_vector ( 3 downto 0 ) |
| s2_h | std_logic_vector ( 3 downto 0 ) |
| s1_h | std_logic_vector ( 3 downto 0 ) |
| s4_h | std_logic_vector ( 2 downto 0 ) |
| COMP_DONE_r | std_logic |
| ctrl_Dqs_Rst_r1 | std_logic |
| ctrl_Dqs_En_r1 | std_logic |
| ctrl_WrEn_r1 | std_logic |
| ctrl_RdEn_r1 | std_logic |
| ddr2_cs_r_out | std_logic |
| ddr2_cs_r_odt | std_logic |
| count6 | std_logic_vector ( 5 downto 0 ) |
Attributes | |
| equivalent_register_removal | string |
| equivalent_register_removal | " no " |
Detailed Description
Main RAM controller module.This module is the main control logic of the memory interface. All commands are issued from here acoording to the burst, CAS Latency and the user commands.
Definition at line 94 of file ddr2_mem_ddr2_controller.vhd.
Member Function Documentation
| PROCESS_100 | ( RD , | |
| RD_r , | ||
| WR , | ||
| WR_r , | ||
| LMR_r , | ||
| PRE_r , | ||
| ACT_r , | ||
| REF_r , | ||
| auto_ref , | ||
| chip_cnt , | ||
| auto_cnt , | ||
| conflict_detect , | ||
| conflict_detect_r , | ||
| conflict_resolved_r , | ||
| count_200cycle_done_r , | ||
| idle_cnt , | ||
| init_count , | ||
| init_memory , | ||
| mrd_count , | ||
| LMR_PRE_REF_ACT_cmd_r , | ||
| phy_Dly_Slct_Done , | ||
| ras_count , | ||
| rcd_count , | ||
| rd_to_wr_count , | ||
| read_burst_cnt , | ||
| rfc_count , | ||
| rp_count , | ||
| rtp_count , | ||
| pre_cnt , | ||
| state , | ||
| wr_to_rd_count , | ||
| wrburst_cnt , | ||
| wtp_count , | ||
| done_200us , | ||
| cs_width1 , | ||
| dummy_write_flag_r , | ||
| COMP_DONE_r , | ||
| init_done , | ||
| af_empty_r ) |
main control state machine
Definition at line 1524 of file ddr2_mem_ddr2_controller.vhd.
01524 process(RD, RD_r, WR, WR_r, LMR_r, PRE_r, ACT_r, REF_r, 01525 auto_ref, chip_cnt, auto_cnt, conflict_detect, conflict_detect_r, 01526 conflict_resolved_r, count_200cycle_done_r, idle_cnt, 01527 init_count, init_memory, mrd_count, LMR_PRE_REF_ACT_cmd_r, 01528 phy_Dly_Slct_Done, ras_count, rcd_count, rd_to_wr_count, 01529 read_burst_cnt, rfc_count, rp_count, rtp_count, pre_cnt, --- Precharge fix for deep memory 01530 state, wr_to_rd_count, wrburst_cnt, wtp_count, done_200us, 01531 cs_width1, dummy_write_flag_r, COMP_DONE_r, init_done, af_empty_r) 01532 begin 01533 next_state <= state; 01534 case state is 01535 when IDLE => 01536 if ((conflict_detect_r = '1' or LMR_PRE_REF_ACT_cmd_r = '1' or auto_ref = '1') and ras_count = "0000" and init_done = '1') then 01537 next_state <= PRECHARGE; 01538 elsif ((WR_r = '1' or RD_r = '1') and (ras_count = "0000")) then 01539 next_state <= ACTIVE; 01540 end if; 01541 01542 when PRECHARGE => 01543 next_state <= PRECHARGE_WAIT; 01544 01545 -- Precharge fix for deep memory 01546 when PRECHARGE_WAIT => 01547 if (rp_count = "000") then 01548 if (auto_ref = '1' or REF_r = '1') then 01549 if ((pre_cnt < cs_width1) and init_memory = '0')then 01550 next_state <= PRECHARGE; 01551 else 01552 next_state <= AUTO_REFRESH; 01553 end if; 01554 elsif (LMR_r = '1') then 01555 next_state <= LOAD_MODE; 01556 elsif (conflict_detect_r = '1' or ACT_r = '1') then 01557 next_state <= ACTIVE; 01558 else 01559 next_state <= IDLE; 01560 end if; 01561 else 01562 next_state <= PRECHARGE_WAIT; 01563 end if; 01564 01565 when LOAD_MODE => 01566 next_state <= MODE_REGISTER_WAIT; 01567 01568 when MODE_REGISTER_WAIT => 01569 if (mrd_count = '0') then 01570 next_state <= IDLE; 01571 else 01572 next_state <= MODE_REGISTER_WAIT; 01573 end if; 01574 01575 when AUTO_REFRESH => 01576 next_state <= AUTO_REFRESH_WAIT; 01577 01578 when AUTO_REFRESH_WAIT => 01579 if ((auto_cnt < cs_width1) and rfc_count = "000001" and init_memory = '0')then 01580 next_state <= AUTO_REFRESH; 01581 elsif ((rfc_count = "000001") and (conflict_detect_r = '1')) then 01582 next_state <= ACTIVE; 01583 elsif (rfc_count = "000001") then 01584 next_state <= IDLE; 01585 else 01586 next_state <= AUTO_REFRESH_WAIT; 01587 end if; 01588 01589 when ACTIVE => 01590 next_state <= ACTIVE_WAIT; 01591 01592 when ACTIVE_WAIT => 01593 if (rcd_count = "000") then -- first active or when a new row is opened 01594 if (WR = '1') then 01595 next_state <= FIRST_WRITE; 01596 elsif (RD = '1') then 01597 next_state <= FIRST_READ; 01598 else 01599 next_state <= IDLE; 01600 end if; 01601 else 01602 next_state <= ACTIVE_WAIT; 01603 end if; 01604 01605 when FIRST_WRITE => 01606 next_state <= WRITE_WAIT; 01607 01608 when BURST_WRITE => 01609 next_state <= WRITE_WAIT; 01610 01611 when WRITE_WAIT => 01612 if (((conflict_detect = '1') and (conflict_resolved_r = '0')) or (auto_ref = '1')) then 01613 if ((wtp_count = "0000") and (ras_count = "0000")) then 01614 next_state <= PRECHARGE; 01615 else 01616 next_state <= WRITE_WAIT; 01617 end if; 01618 elsif (RD = '1') then 01619 next_state <= WRITE_READ; 01620 elsif ((WR = '1') and (wrburst_cnt = "010")) then 01621 next_state <= BURST_WRITE; 01622 elsif ((WR = '1') and (wrburst_cnt = "000")) then --added to improve the efficiency 01623 next_state <= FIRST_WRITE; 01624 elsif (idle_cnt = "0000") then 01625 next_state <= PRECHARGE; 01626 else 01627 next_state <= WRITE_WAIT; 01628 end if; 01629 01630 when WRITE_READ => 01631 if (wr_to_rd_count = "0000") then 01632 next_state <= FIRST_READ; 01633 else 01634 next_state <= WRITE_READ; 01635 end if; 01636 01637 when FIRST_READ => 01638 next_state <= READ_WAIT; 01639 01640 when BURST_READ => 01641 next_state <= READ_WAIT; 01642 01643 when READ_WAIT => 01644 if (((conflict_detect = '1') and (conflict_resolved_r = '0')) or (auto_ref = '1')) then 01645 if(rtp_count = "0000" and ras_count = "0000") then 01646 next_state <= PRECHARGE; 01647 else 01648 next_state <= READ_WAIT; 01649 end if; 01650 elsif (WR = '1')then 01651 next_state <= READ_WRITE; 01652 elsif ((RD = '1') and (read_burst_cnt <= "010")) then 01653 if(af_empty_r = '1') then 01654 next_state <= FIRST_READ; 01655 else 01656 next_state <= BURST_READ; 01657 end if; 01658 elsif (idle_cnt = "0000") then 01659 next_state <= PRECHARGE; 01660 else 01661 next_state <= READ_WAIT; 01662 end if; 01663 01664 when READ_WRITE => 01665 if (rd_to_wr_count = "0000") then 01666 next_state <= FIRST_WRITE; 01667 else 01668 next_state <= READ_WRITE; 01669 end if; 01670 01671 when others => next_state <= IDLE; 01672 01673 end case; 01674 end process;
| PROCESS_101 | ( clk0 ) |
register command outputs
Definition at line 1677 of file ddr2_mem_ddr2_controller.vhd.
01677 process(clk0) 01678 begin 01679 if (clk0 = '1' and clk0'event) then 01680 if (rst = '1') then 01681 state_r2 <= idle; 01682 state_r3 <= idle; 01683 init_state_r2 <= "00000"; 01684 else 01685 state_r2 <= state; 01686 state_r3 <= state_r2; 01687 init_state_r2 <= init_state; 01688 end if; 01689 end if; 01690 end process;
| PROCESS_102 | ( clk0 ) |
commands to the memory
Definition at line 1693 of file ddr2_mem_ddr2_controller.vhd.
01693 process(clk0) 01694 begin 01695 if (clk0 = '1' and clk0'event) then 01696 if (rst = '1') then 01697 ddr2_ras_r <= '1'; 01698 elsif (state = LOAD_MODE or state = PRECHARGE or state = ACTIVE or state = AUTO_REFRESH 01699 or init_state = INIT_LOAD_MODE or init_state = INIT_PRECHARGE or init_state = INIT_ACTIVE or init_state = INIT_AUTO_REFRESH 01700 or init_state = INIT_DUMMY_ACTIVE) then 01701 ddr2_ras_r <= '0'; 01702 else 01703 ddr2_ras_r <= '1'; 01704 end if; 01705 end if; 01706 end process;
| PROCESS_103 | ( clk0 ) |
commands to the memory
Definition at line 1709 of file ddr2_mem_ddr2_controller.vhd.
01709 process(clk0) 01710 begin 01711 if (clk0 = '1' and clk0'event) then 01712 if (rst = '1') then 01713 ddr2_cas_r <= '1'; 01714 elsif (state = LOAD_MODE or state = FIRST_WRITE or state = BURST_WRITE or 01715 state = FIRST_READ or state = BURST_READ or init_state = INIT_DUMMY_FIRST_READ or 01716 init_state = INIT_LOAD_MODE or init_state = INIT_AUTO_REFRESH or 01717 state = AUTO_REFRESH or init_state = INIT_DUMMY_READ or init_state = INIT_PATTERN_READ or init_state = INIT_PATTERN_WRITE) then 01718 ddr2_cas_r <= '0'; 01719 else 01720 ddr2_cas_r <= '1'; 01721 end if; 01722 end if; 01723 end process;
| PROCESS_104 | ( clk0 ) |
commands to the memory
Definition at line 1726 of file ddr2_mem_ddr2_controller.vhd.
01726 process(clk0) 01727 begin 01728 if (clk0 = '1' and clk0'event) then 01729 if (rst = '1') then 01730 ddr2_we_r <= '1'; 01731 elsif (state = LOAD_MODE or state = PRECHARGE or state = FIRST_WRITE or state = BURST_WRITE or init_state = INIT_PATTERN_WRITE 01732 or init_state = INIT_LOAD_MODE or init_state = INIT_PRECHARGE) then 01733 ddr2_we_r <= '0'; 01734 else 01735 ddr2_we_r <= '1'; 01736 end if; 01737 end if; 01738 end process;
| PROCESS_105 | ( clk0 ) |
register commands to the memory
Definition at line 1741 of file ddr2_mem_ddr2_controller.vhd.
01741 process(clk0) 01742 begin 01743 if (clk0 = '1' and clk0'event) then 01744 if (rst = '1') then 01745 ddr2_ras_r2 <= '1'; 01746 ddr2_cas_r2 <= '1'; 01747 ddr2_we_r2 <= '1'; 01748 else 01749 ddr2_ras_r2 <= ddr2_ras_r; 01750 ddr2_cas_r2 <= ddr2_cas_r; 01751 ddr2_we_r2 <= ddr2_we_r; 01752 end if; 01753 end if; 01754 end process;
| PROCESS_106 | ( clk0 ) |
register commands to the memory
Definition at line 1757 of file ddr2_mem_ddr2_controller.vhd.
01757 process(clk0) 01758 begin 01759 if (clk0 = '1' and clk0'event) then 01760 if (rst = '1') then 01761 ddr2_ras_r3 <= '1'; 01762 ddr2_cas_r3 <= '1'; 01763 ddr2_we_r3 <= '1'; 01764 else 01765 ddr2_ras_r3 <= ddr2_ras_r2; 01766 ddr2_cas_r3 <= ddr2_cas_r2; 01767 ddr2_we_r3 <= ddr2_we_r2; 01768 end if; -- else: !if(rst) 01769 end if; 01770 end process;
| PROCESS_107 | ( clk0 ) |
build address
Definition at line 1773 of file ddr2_mem_ddr2_controller.vhd.
01773 process(clk0) 01774 begin 01775 if (clk0 = '1' and clk0'event) then 01776 if (rst = '1') then 01777 row_addr_r((row_address-1) downto 0) <= (others => '0'); 01778 else 01779 row_addr_r((row_address-1) downto 0) <= af_addr(((row_address + col_ap_width)-1) downto col_ap_width); 01780 end if; 01781 end if; 01782 end process;
| PROCESS_108 | ( clk0 ) |
chip enable generation logic
Definition at line 1785 of file ddr2_mem_ddr2_controller.vhd.
01785 process(clk0) 01786 begin 01787 if (clk0 = '1' and clk0'event) then 01788 if (rst = '1') then 01789 ddr2_cs_r <= '0'; 01790 else 01791 if (af_addr_r((chip_address + bank_address +row_address + (col_ap_width-1)) downto (bank_address + row_address + col_ap_width)) = 01792 cs_h0((chip_address - 1) downto 0)) then 01793 ddr2_cs_r <= cs_hE(0); 01794 elsif (af_addr_r((chip_address + bank_address + row_address + (col_ap_width-1)) downto (bank_address +row_address + col_ap_width)) = 01795 cs_h1((chip_address - 1) downto 0)) then 01796 ddr2_cs_r <= cs_hD(0); 01797 elsif (af_addr_r((chip_address + bank_address +row_address + (col_ap_width-1)) downto (bank_address + row_address + col_ap_width)) = 01798 cs_h2((chip_address - 1) downto 0)) then 01799 ddr2_cs_r <= cs_hB(0); 01800 elsif (af_addr_r((chip_address + bank_address +row_address + (col_ap_width-1)) downto (bank_address + row_address + col_ap_width)) = 01801 cs_h3((chip_address - 1) downto 0)) then 01802 ddr2_cs_r <= cs_h7(0); 01803 else 01804 ddr2_cs_r <= cs_hF(0); 01805 end if; 01806 end if; 01807 end if; 01808 end process;
| PROCESS_109 | ( clk0 ) |
address during init
Definition at line 1811 of file ddr2_mem_ddr2_controller.vhd.
01811 process(clk0) 01812 begin 01813 if (clk0 = '1' and clk0'event) then 01814 if (rst = '1') then 01815 ddr2_address_init_r <= (others => '0'); 01816 else 01817 if (init_state_r2 = INIT_PRECHARGE) then 01818 ddr2_address_init_r <= (10 => '1' , others => '0'); -- *A10 = 1 for precharge all * 01819 elsif (init_state_r2 = INIT_LOAD_MODE and init_count_cp = "0101") then 01820 ddr2_address_init_r <= ext_mode_reg; -- A0 == 0 for DLL enable 01821 elsif (init_state_r2 = INIT_LOAD_MODE and init_count_cp = "0110") then 01822 ddr2_address_init_r <= add_const1((row_address-1) downto 0) or load_mode_reg; 01823 elsif (init_state_r2 = INIT_LOAD_MODE and init_count_cp = "1010") then 01824 ddr2_address_init_r <= load_mode_reg; -- Write recovery = 4; cas_latency = 4; burst length = 4 01825 elsif (init_state_r2 = INIT_LOAD_MODE and init_count_cp = "1011") then 01826 ddr2_address_init_r <= (add_const2((row_address-1) downto 0) or ext_mode_reg); -- OCD DEFAULT 01827 elsif (init_state_r2 = INIT_LOAD_MODE and init_count_cp = "1100") then 01828 ddr2_address_init_r <= (add_const3((row_address-1) downto 0) or ext_mode_reg); -- OCD EXIT 01829 elsif(init_state_r2 = INIT_DUMMY_ACTIVE) then 01830 ddr2_address_init_r <= row_addr_r; 01831 else 01832 ddr2_address_init_r <= (others => '0'); 01833 end if; 01834 end if; 01835 end if; 01836 end process;
| PROCESS_110 | ( clk0 ) |
address assembly
Definition at line 1839 of file ddr2_mem_ddr2_controller.vhd.
01839 process(clk0) 01840 begin 01841 if (clk0 = '1' and clk0'event) then 01842 if (rst = '1') then 01843 ddr2_address_r1 <= (others => '0'); 01844 elsif ((state_r2 = ACTIVE)) then 01845 ddr2_address_r1 <= row_addr_r; 01846 elsif (state_r2 = FIRST_WRITE or state_r2 = BURST_WRITE or 01847 state_r2 = FIRST_READ or state_r2 = BURST_READ) then 01848 ddr2_address_r1 <= af_addr_r1((row_address-1) downto 0) and add_const4((row_address-1) downto 0); 01849 elsif (state_r2 = PRECHARGE) then 01850 if(PRE_r = '1') then 01851 ddr2_address_r1 <= af_addr_r1((row_address-1) downto 0); 01852 else 01853 ddr2_address_r1 <= (10 => '1', others => '0'); 01854 end if; 01855 elsif (state_r2 = LOAD_MODE) then 01856 ddr2_address_r1 <= af_addr_r1((row_address-1) downto 0); 01857 else 01858 ddr2_address_r1 <= (others => '0'); 01859 end if; 01860 end if; 01861 end process;
| PROCESS_111 | ( clk0 ) |
register address to RAM
Definition at line 1864 of file ddr2_mem_ddr2_controller.vhd.
01864 process(clk0) 01865 begin 01866 if (clk0 = '1' and clk0'event) then 01867 if (rst = '1') then 01868 ddr2_address_r2 <= (others => '0'); 01869 elsif (init_memory = '1') then 01870 ddr2_address_r2 <= ddr2_address_init_r; 01871 else 01872 ddr2_address_r2 <= ddr2_address_r1; 01873 end if; 01874 end if; 01875 end process;
| PROCESS_112 | ( clk0 ) |
bank address during init
Definition at line 1878 of file ddr2_mem_ddr2_controller.vhd.
01878 process(clk0) 01879 begin 01880 if (clk0 = '1' and clk0'event) then 01881 if (rst = '1') then 01882 ddr2_ba_r1((bank_address-1) downto 0) <= (others => '0'); 01883 elsif ((init_memory = '1') and (init_state_r2 = INIT_LOAD_MODE)) then 01884 if (init_count_cp = X"3") then 01885 ddr2_ba_r1((bank_address-1) downto 0) <= (1 => '1', others => '0'); -- emr2 01886 elsif (init_count_cp = X"4") then 01887 ddr2_ba_r1((bank_address-1) downto 0) <= (0 | 1 => '1', others => '0'); -- emr3 01888 elsif (init_count_cp = X"5" or init_count_cp = X"B" or init_count_cp = X"C") then 01889 ddr2_ba_r1((bank_address-1) downto 0) <= (0 => '1', others => '0'); -- emr 01890 else 01891 ddr2_ba_r1((bank_address-1) downto 0) <= (others => '0'); 01892 end if; 01893 elsif ((state_r2 = ACTIVE) or (init_state_r2 = INIT_DUMMY_ACTIVE) or (state_r2 = LOAD_MODE) or ((state_r2 = PRECHARGE) and (PRE_r = '1')) 01894 or (init_state_r2 = INIT_ACTIVE) or (init_state_r2 = INIT_LOAD_MODE) or (init_state_r2 = INIT_PRECHARGE)) then 01895 ddr2_ba_r1((bank_address-1) downto 0) <= af_addr_r(((bank_address + row_address + col_ap_width)-1) downto (col_ap_width + row_address)); 01896 else 01897 ddr2_ba_r1((bank_address-1) downto 0) <= ddr2_ba_r1((bank_address-1) downto 0); 01898 end if; 01899 end if; 01900 end process;
| PROCESS_113 | ( clk0 ) |
register bank address to RAM
Definition at line 1903 of file ddr2_mem_ddr2_controller.vhd.
01903 process(clk0) 01904 begin 01905 if (clk0 = '1' and clk0'event) then 01906 if (rst = '1') then 01907 ddr2_ba_r2((bank_address-1) downto 0) <= (others => '0'); 01908 else 01909 ddr2_ba_r2((bank_address-1) downto 0) <= ddr2_ba_r1; 01910 end if; 01911 end if; 01912 end process;
| PROCESS_114 | ( clk0 ) |
MUX chip select.
Definition at line 1915 of file ddr2_mem_ddr2_controller.vhd.
01915 process(clk0) 01916 begin 01917 if (clk0 = '1' and clk0'event) then 01918 if (rst = '1') then 01919 ddr2_cs_r1 <= '1'; 01920 elsif (init_memory = '1') then 01921 if (chip_cnt = "00") then 01922 ddr2_cs_r1 <= cs_hE(0); 01923 elsif (chip_cnt = "01") then 01924 ddr2_cs_r1 <= cs_hD(0); 01925 elsif (chip_cnt = "10") then 01926 ddr2_cs_r1 <= cs_hB(0); 01927 elsif (chip_cnt = "11") then 01928 ddr2_cs_r1 <= cs_h7(0); 01929 else 01930 ddr2_cs_r1 <= cs_hF(0); 01931 end if; 01932 --- Precharge fix for deep memory 01933 elsif (state_r2 = PRECHARGE) then 01934 if (pre_cnt = "001") then 01935 ddr2_cs_r1 <= cs_hE(0); 01936 elsif (pre_cnt = "010") then 01937 ddr2_cs_r1 <= cs_hD(0); 01938 elsif (pre_cnt = "011") then 01939 ddr2_cs_r1 <= cs_hB(0); 01940 elsif (pre_cnt = "100") then 01941 ddr2_cs_r1 <= cs_h7(0); 01942 elsif (pre_cnt = "000") then 01943 ddr2_cs_r1 <= ddr2_cs_r1; --cs_hF 01944 else 01945 ddr2_cs_r1 <= cs_hF(0); 01946 end if; 01947 elsif (state_r2 = AUTO_REFRESH) then 01948 if (auto_cnt = "001") then 01949 ddr2_cs_r1 <= cs_hE(0); 01950 elsif (auto_cnt = "010") then 01951 ddr2_cs_r1 <= cs_hD(0); 01952 elsif (auto_cnt = "011") then 01953 ddr2_cs_r1 <= cs_hB(0); 01954 elsif (auto_cnt = "100") then 01955 ddr2_cs_r1 <= cs_h7(0); 01956 else 01957 ddr2_cs_r1 <= cs_hF(0); 01958 end if; 01959 elsif ((state_r2 = ACTIVE) or (init_state_r2 = INIT_DUMMY_ACTIVE) or (state_r2 = LOAD_MODE) or (state_r2 = PRECHARGE_WAIT) 01960 or (init_state_r2 = INIT_ACTIVE) or (init_state_r2 = INIT_LOAD_MODE) or (init_state_r2 = INIT_PRECHARGE_WAIT)) then 01961 ddr2_cs_r1 <= ddr2_cs_r; 01962 else 01963 ddr2_cs_r1 <= ddr2_cs_r1; 01964 end if; 01965 end if; 01966 end process;
| PROCESS_115 | ( clk0 ) |
register chip select to RAM
Definition at line 1969 of file ddr2_mem_ddr2_controller.vhd.
01969 process(clk0) 01970 begin 01971 if (clk0 = '1' and clk0'event) then 01972 if (rst = '1') then 01973 ddr2_cs_r_out <= '1'; 01974 ddr2_cs_r_odt <= '1'; 01975 else 01976 ddr2_cs_r_out <= ddr2_cs_r1; 01977 ddr2_cs_r_odt <= ddr2_cs_r1; 01978 end if; 01979 end if; 01980 end process;
| PROCESS_116 | ( clk0 ) |
???
Definition at line 1983 of file ddr2_mem_ddr2_controller.vhd.
01983 process(clk0) 01984 begin 01985 if (clk0 = '1' and clk0'event) then 01986 if (rst = '1') then 01987 conflict_resolved_r <= '0'; 01988 else 01989 if ((state = PRECHARGE_WAIT) and (conflict_detect_r = '1')) then 01990 conflict_resolved_r <= '1'; 01991 elsif(af_rden = '1') then 01992 conflict_resolved_r <= '0'; 01993 end if; 01994 end if; 01995 end if; 01996 end process;
| PROCESS_117 | ( clk0 ) |
register clock enable to RAM
Definition at line 1999 of file ddr2_mem_ddr2_controller.vhd.
01999 process(clk0) 02000 begin 02001 if (clk0 = '1' and clk0'event) then 02002 if (rst = '1') then 02003 ddr2_cke_r <= cs_h0(0); 02004 elsif (done_200us = '1') then 02005 ddr2_cke_r <= cs_hF(0); 02006 end if; 02007 end if; 02008 end process;
| PROCESS_118 | ( clk0 ) |
odt
Definition at line 2011 of file ddr2_mem_ddr2_controller.vhd.
02011 process(clk0) 02012 begin 02013 if (clk0 = '1' and clk0'event) then 02014 if (rst = '1') then 02015 odt_en_cnt <= "0000"; 02016 elsif((state = FIRST_WRITE) and (ODT_ENABLE = '1')) then 02017 odt_en_cnt <= (('0' & ADDITIVE_LATENCY_VALUE) + ('0' & CAS_LATENCY_VALUE) - "0010"); 02018 elsif((state = FIRST_READ) and (ODT_ENABLE = '1')) then 02019 odt_en_cnt <= (('0' & ADDITIVE_LATENCY_VALUE) + ('0' & CAS_LATENCY_VALUE)- "0001"); 02020 elsif(odt_en_cnt /= "0000") then 02021 odt_en_cnt <= odt_en_cnt - "0001"; 02022 else 02023 odt_en_cnt <= "0000"; 02024 end if; 02025 end if; 02026 end process;
| PROCESS_119 | ( clk0 ) |
odt count
Definition at line 2029 of file ddr2_mem_ddr2_controller.vhd.
02029 process(clk0) 02030 begin 02031 if (clk0 = '1' and clk0'event) then 02032 if (rst = '1') then 02033 odt_cnt <= "0000"; 02034 elsif((state = FIRST_WRITE) or (state = BURST_WRITE)) then 02035 odt_cnt <= (('0' & ADDITIVE_LATENCY_VALUE) + ('0'& CAS_LATENCY_VALUE) + ('0' & burst_cnt)); 02036 elsif((state = FIRST_READ) or (state = BURST_READ)) then 02037 odt_cnt <= (('0' & ADDITIVE_LATENCY_VALUE) + ('0' & CAS_LATENCY_VALUE) + ('0' & burst_cnt) + "0001"); 02038 elsif(odt_cnt /= "0000") then 02039 odt_cnt <= odt_cnt - "0001"; 02040 else 02041 odt_cnt <= "0000"; 02042 end if; 02043 end if; 02044 end process;
| PROCESS_120 | ( rst , | |
| odt_en_cnt , | ||
| odt_cnt ) |
odt_en logic is made combinational to add a flop to the ctrl_odt logic
Definition at line 2047 of file ddr2_mem_ddr2_controller.vhd.
02047 process(rst, odt_en_cnt, odt_cnt) 02048 begin 02049 if (rst = '1') then 02050 odt_en <= '0'; 02051 elsif(odt_en_cnt = "0001") then 02052 odt_en <= cs_hF(0); 02053 elsif(odt_cnt > "0010" and odt_en_cnt <= "0001") then 02054 odt_en <= cs_hF(0); 02055 elsif (odt_cnt = "0010") then 02056 odt_en <= '0'; 02057 else 02058 odt_en <= '0'; 02059 end if; 02060 end process;
| PROCESS_121 | ( clk0 ) |
added for deep designs
Definition at line 2063 of file ddr2_mem_ddr2_controller.vhd.
02063 process(clk0) 02064 begin 02065 if (clk0 = '1' and clk0'event) then 02066 if (rst = '1') then 02067 ctrl_odt <= '0'; 02068 else 02069 case cs_width is 02070 when 1 => 02071 if (ddr2_cs_r_odt = cs_h0(0)) then 02072 ctrl_odt <= (odt_en and cs_h1(0)); 02073 else 02074 ctrl_odt <= '0'; 02075 end if; 02076 02077 when 2 => 02078 if (ddr2_cs_r_odt = cs_h2(0)) then 02079 ctrl_odt <= (odt_en and cs_hA(0)); 02080 elsif (ddr2_cs_r_odt = cs_h1(0)) then 02081 ctrl_odt <= (odt_en and cs_h1(0)); 02082 else 02083 ctrl_odt <= '0'; 02084 end if; 02085 02086 when 3 => 02087 if (ddr2_cs_r_odt = cs_h6(0)) then 02088 ctrl_odt <= (odt_en and cs_D100(0)); 02089 elsif(ddr2_cs_r_odt = cs_h5(0)) then 02090 ctrl_odt <= (odt_en and cs_D100(0)); 02091 elsif (ddr2_cs_r_odt = cs_h3(0)) then 02092 ctrl_odt <= (odt_en and cs_hA(0)); 02093 else 02094 ctrl_odt <= '0'; 02095 end if; 02096 02097 when 4 => 02098 if (ddr2_cs_r_odt = cs_hE(0)) then 02099 ctrl_odt <= (odt_en and cs_D1000(0)); 02100 elsif (ddr2_cs_r_odt = cs_hD(0)) then 02101 ctrl_odt <= (odt_en and cs_D1000(0)); 02102 elsif (ddr2_cs_r_odt = cs_hB(0)) then 02103 ctrl_odt <= (odt_en and cs_D1000(0)); 02104 elsif (ddr2_cs_r_odt = cs_h7(0)) then 02105 ctrl_odt <= (odt_en and cs_D100(0)); 02106 else 02107 ctrl_odt <= '0'; 02108 end if; 02109 02110 when others => ctrl_odt <= ctrl_odt; 02111 02112 end case; 02113 end if; 02114 end if; 02115 end process;
| PROCESS_42 | ( command_address , | |
| ctrl_init_done , | ||
| af_empty ) |
commands
Definition at line 338 of file ddr2_mem_ddr2_controller.vhd.
00338 process(command_address, ctrl_init_done, af_empty) 00339 begin 00340 WR <= '0'; 00341 RD <= '0'; 00342 LMR <= '0'; 00343 PRE <= '0'; 00344 REF <= '0'; 00345 ACT <= '0'; 00346 if (ctrl_init_done = '1' and af_empty = '0') then 00347 case command_address is 00348 when "000" => LMR <= '1'; 00349 when "001" => REF <= '1'; 00350 when "010" => PRE <= '1'; 00351 when "011" => ACT <= '1'; 00352 when "100" => WR <= '1'; 00353 when "101" => RD <= '1'; 00354 when others => null; 00355 end case; 00356 end if; 00357 end process;
| PROCESS_43 | ( clk0 ) |
register address outputs
Definition at line 360 of file ddr2_mem_ddr2_controller.vhd.
00360 process(clk0) 00361 begin 00362 if (clk0 = '1' and clk0'event) then 00363 if (rst = '1') then 00364 WR_r <= '0'; 00365 RD_r <= '0'; 00366 LMR_r <= '0'; 00367 PRE_r <= '0'; 00368 REF_r <= '0'; 00369 ACT_r <= '0'; 00370 af_empty_r <= '0'; 00371 LMR_PRE_REF_ACT_cmd_r <= '0'; 00372 else 00373 WR_r <= WR; 00374 RD_r <= RD; 00375 LMR_r <= LMR; 00376 PRE_r <= PRE; 00377 REF_r <= REF; 00378 ACT_r <= ACT; 00379 af_empty_r <= af_empty; 00380 LMR_PRE_REF_ACT_cmd_r <= LMR or PRE or REF or ACT; 00381 end if; 00382 end if; 00383 end process;
| PROCESS_44 | ( clk0 ) |
register address outputs
Definition at line 386 of file ddr2_mem_ddr2_controller.vhd.
00386 process(clk0) 00387 begin 00388 if (clk0 = '1' and clk0'event) then 00389 if (rst = '1') then 00390 af_addr_r <= (others => '0'); 00391 af_addr_r1 <= (others => '0'); 00392 conflict_detect_r <= '0'; 00393 else 00394 af_addr_r <= af_addr; 00395 af_addr_r1 <= af_addr_r; 00396 conflict_detect_r <= conflict_detect; 00397 end if; 00398 end if; 00399 end process;
| PROCESS_47 | ( clk0 ) |
to initialize memory
Definition at line 424 of file ddr2_mem_ddr2_controller.vhd.
00424 process(clk0) 00425 begin 00426 if (clk0 = '1' and clk0'event) then 00427 if ((rst = '1') or (init_state = INIT_DEEP_MEMORY_ST)) then 00428 init_memory <= '1'; 00429 elsif (init_count_cp = "1111") then 00430 init_memory <= '0'; 00431 else 00432 init_memory <= init_memory; 00433 end if; 00434 end if; 00435 end process;
| PROCESS_48 | ( clk0 ) |
mrd count
Definition at line 438 of file ddr2_mem_ddr2_controller.vhd.
00438 process(clk0) 00439 begin 00440 if (clk0 = '1' and clk0'event) then 00441 if (rst = '1') then 00442 mrd_count <= '0'; 00443 elsif (state = LOAD_MODE) then 00444 mrd_count <= mrd_count_value; 00445 elsif (mrd_count /= '0') then 00446 mrd_count <= '0'; 00447 else 00448 mrd_count <= '0'; 00449 end if; 00450 end if; 00451 end process;
| PROCESS_49 | ( clk0 ) |
rp count
Definition at line 454 of file ddr2_mem_ddr2_controller.vhd.
00454 process(clk0) 00455 begin 00456 if (clk0 = '1' and clk0'event) then 00457 if (rst = '1') then 00458 rp_count(2 downto 0) <= "000"; 00459 elsif (state = PRECHARGE) then 00460 rp_count(2 downto 0) <= rp_count_value; 00461 elsif (rp_count(2 downto 0) /= "000") then 00462 rp_count(2 downto 0) <= rp_count(2 downto 0) - "001"; 00463 else 00464 rp_count(2 downto 0) <= "000"; 00465 end if; 00466 end if; 00467 end process;
| PROCESS_50 | ( clk0 ) |
rfc count
Definition at line 470 of file ddr2_mem_ddr2_controller.vhd.
00470 process(clk0) 00471 begin 00472 if (clk0 = '1' and clk0'event) then 00473 if (rst = '1') then 00474 rfc_count(5 downto 0) <= (others => '0'); 00475 elsif (state = AUTO_REFRESH) then 00476 rfc_count(5 downto 0) <= rfc_count_value; 00477 elsif (rfc_count(5 downto 0) /= "000000") then 00478 rfc_count(5 downto 0) <= rfc_count(5 downto 0) - "000001"; 00479 else 00480 rfc_count(5 downto 0) <= "000000"; 00481 end if; 00482 end if; 00483 end process;
| PROCESS_51 | ( clk0 ) |
rcd count - 20ns
Definition at line 486 of file ddr2_mem_ddr2_controller.vhd.
00486 process(clk0) 00487 begin 00488 if (clk0 = '1' and clk0'event) then 00489 if (rst = '1') then 00490 rcd_count(2 downto 0) <= "000"; 00491 elsif (state = ACTIVE) then 00492 rcd_count(2 downto 0) <= rcd_count_value - ADDITIVE_LATENCY_VALUE - "001"; 00493 elsif (rcd_count(2 downto 0) /= "000") then 00494 rcd_count(2 downto 0) <= rcd_count(2 downto 0) - "001"; 00495 else 00496 rcd_count(2 downto 0) <= "000"; 00497 end if; 00498 end if; 00499 end process;
| PROCESS_52 | ( clk0 ) |
ras count - active to precharge
Definition at line 502 of file ddr2_mem_ddr2_controller.vhd.
00502 process(clk0) 00503 begin 00504 if (clk0 = '1' and clk0'event) then 00505 if (rst = '1') then 00506 ras_count(3 downto 0) <= "0000"; 00507 elsif (state = ACTIVE) then 00508 ras_count(3 downto 0) <= ras_count_value; 00509 elsif (ras_count(3 downto 1) = "000") then 00510 if (ras_count(0) /= '0') then 00511 ras_count(0) <= '0'; 00512 end if; 00513 else 00514 ras_count(3 downto 0) <= ras_count(3 downto 0) - "0001"; 00515 end if; 00516 end if; 00517 end process;
| PROCESS_53 | ( clk0 ) |
AL+BL/2+TRTP-2 rtp count - read to precharge
Definition at line 521 of file ddr2_mem_ddr2_controller.vhd.
00521 process(clk0) 00522 begin 00523 if (clk0 = '1' and clk0'event) then 00524 if (rst = '1') then 00525 rtp_count(3 downto 0) <= "0000"; 00526 elsif ((state = FIRST_READ) or (state = BURST_READ)) then 00527 rtp_count(3 downto 0) <= (('0' & trtp_count_value) + ('0' & burst_cnt) + ('0' & ADDITIVE_LATENCY_VALUE) -"0011") ; 00528 elsif (rtp_count(3 downto 1) = "000") then 00529 if (rtp_count(0) /= '0') then 00530 rtp_count(0) <= '0'; 00531 end if; 00532 else 00533 rtp_count(3 downto 0) <= rtp_count(3 downto 0) - "0001"; 00534 end if; 00535 end if; 00536 end process;
| PROCESS_54 | ( clk0 ) |
WL+BL/2+TWR wtp count - write to precharge
Definition at line 540 of file ddr2_mem_ddr2_controller.vhd.
00540 process(clk0) 00541 begin 00542 if (clk0 = '1' and clk0'event) then 00543 if (rst = '1') then 00544 wtp_count(3 downto 0) <= "0000"; 00545 elsif ((state = FIRST_WRITE) or (state = BURST_WRITE)) then 00546 wtp_count(3 downto 0) <= (('0' & twr_count_value) + ('0' & burst_cnt) + ('0' & CAS_LATENCY_VALUE) + ('0' & ADDITIVE_LATENCY_VALUE) -"0011") ; 00547 elsif (wtp_count(3 downto 1) = "000") then 00548 if (wtp_count(0) /= '0') then 00549 wtp_count(0) <= '0'; 00550 end if; 00551 else 00552 wtp_count(3 downto 0) <= wtp_count(3 downto 0) - "0001"; 00553 end if; 00554 end if; 00555 end process;
| PROCESS_55 | ( clk0 ) |
write to read counter write to read includes : write latency + burst time + tWTR
Definition at line 559 of file ddr2_mem_ddr2_controller.vhd.
00559 process(clk0) 00560 begin 00561 if (clk0 = '1' and clk0'event) then 00562 if (rst = '1') then 00563 wr_to_rd_count(3 downto 0) <= "0000"; 00564 elsif ((state = FIRST_WRITE) or (state = BURST_WRITE)) then 00565 wr_to_rd_count(3 downto 0) <= (('0' & twtr_count_value) + ('0' & burst_cnt) + ('0' & ADDITIVE_LATENCY_VALUE) + ('0' & CAS_LATENCY_VALUE) - "0010"); 00566 elsif (wr_to_rd_count(3 downto 0) /= "0000") then 00567 wr_to_rd_count(3 downto 0) <= wr_to_rd_count(3 downto 0) - "0001"; 00568 else 00569 wr_to_rd_count(3 downto 0) <= "0000"; 00570 end if; 00571 end if; 00572 end process;
| PROCESS_56 | ( clk0 ) |
read to write counter
Definition at line 575 of file ddr2_mem_ddr2_controller.vhd.
00575 process(clk0) 00576 begin 00577 if (clk0 = '1' and clk0'event) then 00578 if (rst = '1') then 00579 rd_to_wr_count(3 downto 0) <= "0000"; 00580 elsif ((state = FIRST_READ) or (state = BURST_READ)) then 00581 rd_to_wr_count(3 downto 0) <= (('0' & ADDITIVE_LATENCY_VALUE) + ("000" & REGISTERED_VALUE) + ('0' & burst_cnt)); 00582 elsif (rd_to_wr_count(3 downto 0) /= "0000") then 00583 rd_to_wr_count(3 downto 0) <= rd_to_wr_count(3 downto 0) - "0001"; 00584 else 00585 rd_to_wr_count(3 downto 0) <= "0000"; 00586 end if; 00587 end if; 00588 end process;
| PROCESS_57 | ( refresh_clk ) |
auto refresh interval counter in refresh_clk domain
Definition at line 591 of file ddr2_mem_ddr2_controller.vhd.
00591 process(refresh_clk) 00592 begin 00593 if (refresh_clk = '1' and refresh_clk'event) then 00594 if (rst = '1') then 00595 refi_count <= "00000000"; 00596 elsif (refi_count = max_ref_cnt) then 00597 refi_count <= "00000000"; 00598 else 00599 refi_count <= refi_count + "00000001"; 00600 end if; 00601 end if; 00602 end process;
| PROCESS_58 | ( refi_count , | |
| done_200us ) |
end of 200us flag
Definition at line 605 of file ddr2_mem_ddr2_controller.vhd.
00605 process(refi_count, done_200us) 00606 begin 00607 if ((refi_count = max_ref_cnt) and (done_200us = '1')) then 00608 ref_flag <= '1'; 00609 else 00610 ref_flag <= '0'; 00611 end if; 00612 end process;
| PROCESS_60 | ( clk0 ) |
refresh detect in 266 MHz clock
Definition at line 630 of file ddr2_mem_ddr2_controller.vhd.
00630 process(clk0) 00631 begin 00632 if (clk0 = '1' and clk0'event) then 00633 if (rst = '1') then 00634 ref_flag_266 <= '0'; 00635 ref_flag_266_r <= '0'; 00636 done_200us <= '0'; 00637 else 00638 ref_flag_266 <= ref_flag; 00639 ref_flag_266_r <= ref_flag_266; 00640 if (done_200us = '0') then 00641 if (cke_200us_cnt = "00000") then 00642 done_200us <= '1'; 00643 end if; 00644 end if; 00645 end if; 00646 end if; 00647 end process;
| PROCESS_61 | ( clk0 ) |
refresh flag detect auto_ref high indicates auto_refresh requirement auto_ref is held high until auto refresh command is issued.
Definition at line 652 of file ddr2_mem_ddr2_controller.vhd.
00652 process(clk0) 00653 begin 00654 if (clk0 = '1' and clk0'event) then 00655 if (rst = '1') then 00656 auto_ref <= '0'; 00657 elsif (ref_flag_266 = '1' and ref_flag_266_r = '0') then 00658 auto_ref <= '1'; 00659 elsif (state = AUTO_REFRESH) then 00660 auto_ref <= '0'; 00661 else 00662 auto_ref <= auto_ref; 00663 end if; 00664 end if; 00665 end process;
| PROCESS_62 | ( clk0 ) |
200 clocks counter - count value : C8 required for initialization
Definition at line 669 of file ddr2_mem_ddr2_controller.vhd.
00669 process(clk0) 00670 begin 00671 if (clk0 = '1' and clk0'event) then 00672 if (rst = '1') then 00673 count_200_cycle(7 downto 0) <= "00000000"; 00674 elsif (init_state = INIT_COUNT_200) then 00675 count_200_cycle(7 downto 0) <= X"C8"; 00676 elsif (count_200_cycle(7 downto 0) /= "00000000") then 00677 count_200_cycle(7 downto 0) <= count_200_cycle(7 downto 0) - "00000001"; 00678 else 00679 count_200_cycle(7 downto 0) <= "00000000"; 00680 end if; 00681 end if; 00682 end process;
| PROCESS_63 | ( clk0 ) |
200 clocks counter done flag
Definition at line 685 of file ddr2_mem_ddr2_controller.vhd.
00685 process(clk0) 00686 begin 00687 if (clk0 = '1' and clk0'event) then 00688 if (rst = '1') then 00689 count_200cycle_done_r <= '0'; 00690 elsif ((init_memory = '1') and (count_200_cycle = "00000000")) then 00691 count_200cycle_done_r <= '1'; 00692 else 00693 count_200cycle_done_r <= '0'; 00694 end if; 00695 end if; 00696 end process;
| PROCESS_64 | ( clk0 ) |
init_done flag
Definition at line 699 of file ddr2_mem_ddr2_controller.vhd.
00699 process(clk0) 00700 begin 00701 if (clk0 = '1' and clk0'event) then 00702 if (rst = '1') then 00703 init_done <= '0'; 00704 elsif ((init_count_cp = "1101") and (count_200cycle_done_r = '1') and (Phy_Mode = '0'))then 00705 init_done <= '1'; 00706 elsif ((Phy_Mode = '1') and (COMP_DONE_r = '1') and (count6 = "010100")) then -- Precharge fix after pattern read 00707 init_done <= '1'; 00708 else 00709 init_done <= init_done; 00710 end if; 00711 end if; 00712 end process;
| PROCESS_65 | ( BURST_LENGTH_VALUE ) |
register burst_length
Definition at line 717 of file ddr2_mem_ddr2_controller.vhd.
00717 process(BURST_LENGTH_VALUE) 00718 begin 00719 if (BURST_LENGTH_VALUE = "010") then 00720 burst_cnt <= "010"; 00721 elsif (BURST_LENGTH_VALUE = "011") then 00722 burst_cnt <= "100"; 00723 else 00724 burst_cnt <= "000"; 00725 end if; 00726 end process;
| PROCESS_66 | ( clk0 ) |
init FSM
Definition at line 729 of file ddr2_mem_ddr2_controller.vhd.
00729 process(clk0) 00730 begin 00731 if (clk0 = '1' and clk0'event) then 00732 if ((rst = '1') or (init_state = INIT_DEEP_MEMORY_ST))then 00733 init_count(3 downto 0) <= "0000"; 00734 elsif (init_memory = '1') then 00735 if (init_state = INIT_LOAD_MODE or init_state = INIT_PRECHARGE or init_state = INIT_AUTO_REFRESH or 00736 init_state = INIT_DUMMY_READ_CYCLES or init_state = INIT_COUNT_200 or init_state = INIT_DEEP_MEMORY_ST 00737 or init_state = INIT_PATTERN_WRITE) then 00738 init_count(3 downto 0) <= init_count(3 downto 0) + "0001"; 00739 elsif(init_count = "1111") then 00740 init_count(3 downto 0) <= "0000"; 00741 else 00742 init_count(3 downto 0) <= init_count(3 downto 0); 00743 end if; 00744 end if; 00745 end if; 00746 end process;
| PROCESS_67 | ( clk0 ) |
init FSM
Definition at line 749 of file ddr2_mem_ddr2_controller.vhd.
00749 process(clk0) 00750 begin 00751 if (clk0 = '1' and clk0'event) then 00752 if ((rst = '1') or (init_state = INIT_DEEP_MEMORY_ST)) then 00753 init_count_cp(3 downto 0) <= "0000"; 00754 elsif (init_memory = '1') then 00755 if (init_state = INIT_LOAD_MODE or init_state = INIT_PRECHARGE or init_state = INIT_AUTO_REFRESH or 00756 init_state = INIT_DUMMY_READ_CYCLES or init_state = INIT_COUNT_200 or init_state = INIT_DEEP_MEMORY_ST 00757 or init_state = INIT_PATTERN_WRITE) then 00758 init_count_cp(3 downto 0) <= init_count_cp(3 downto 0) + "0001"; 00759 elsif(init_count_cp = "1111") then 00760 init_count_cp(3 downto 0) <= "0000"; 00761 else 00762 init_count_cp(3 downto 0) <= init_count_cp(3 downto 0); 00763 end if; 00764 end if; 00765 end if; 00766 end process;
| PROCESS_68 | ( clk0 ) |
determine number of chips for deep memories
Definition at line 769 of file ddr2_mem_ddr2_controller.vhd.
00769 process(clk0) 00770 begin 00771 if (clk0 = '1' and clk0'event) then 00772 if (rst = '1') then 00773 chip_cnt <= "00"; 00774 elsif (init_state = INIT_DEEP_MEMORY_ST) then 00775 chip_cnt <= chip_cnt + "01"; 00776 else 00777 chip_cnt <= chip_cnt; 00778 end if; 00779 end if; 00780 end process;
| PROCESS_69 | ( clk0 ) |
auto refresh count
Definition at line 783 of file ddr2_mem_ddr2_controller.vhd.
00783 process(clk0) 00784 begin 00785 if (clk0 = '1' and clk0'event) then 00786 if (rst = '1' or state = PRECHARGE) then 00787 auto_cnt <= "000"; 00788 elsif (state = AUTO_REFRESH and init_memory = '0') then 00789 auto_cnt <= auto_cnt + "001"; 00790 else 00791 auto_cnt <= auto_cnt; 00792 end if; 00793 end if; 00794 end process;
| PROCESS_70 | ( clk0 ) |
Precharge fix for deep memory.
Definition at line 797 of file ddr2_mem_ddr2_controller.vhd.
00797 process(clk0) 00798 begin 00799 if (clk0 = '1' and clk0'event) then 00800 if (rst = '1' or state = auto_refresh) then 00801 pre_cnt <= "000"; 00802 elsif (state = PRECHARGE and init_memory = '0' and auto_ref = '1') then 00803 pre_cnt <= pre_cnt + "001"; 00804 else 00805 pre_cnt <= pre_cnt; 00806 end if; 00807 end if; 00808 end process;
| PROCESS_71 | ( clk0 ) |
write burst count
Definition at line 811 of file ddr2_mem_ddr2_controller.vhd.
00811 process(clk0) 00812 begin 00813 if (clk0 = '1' and clk0'event) then 00814 if (rst = '1') then 00815 wrburst_cnt(2 downto 0) <= "000"; 00816 elsif (state = FIRST_WRITE or state = BURST_WRITE or init_state = INIT_PATTERN_WRITE) then 00817 wrburst_cnt(2 downto 0) <= burst_cnt(2 downto 0); 00818 elsif (wrburst_cnt(2 downto 0) /= "000") then 00819 wrburst_cnt(2 downto 0) <= wrburst_cnt(2 downto 0) - "001"; 00820 else 00821 wrburst_cnt(2 downto 0) <= "000"; 00822 end if; 00823 end if; 00824 end process;
| PROCESS_72 | ( clk0 ) |
read burst count for state machine
Definition at line 827 of file ddr2_mem_ddr2_controller.vhd.
00827 process(clk0) 00828 begin 00829 if (clk0 = '1' and clk0'event) then 00830 if (rst = '1') then 00831 read_burst_cnt(2 downto 0) <= "000"; 00832 elsif (state = FIRST_READ or state = BURST_READ) then 00833 read_burst_cnt(2 downto 0) <= burst_cnt(2 downto 0); 00834 elsif (read_burst_cnt(2 downto 0) /= "000") then 00835 read_burst_cnt(2 downto 0) <= read_burst_cnt(2 downto 0) - "001"; 00836 else 00837 read_burst_cnt(2 downto 0) <= "000"; 00838 end if; 00839 end if; 00840 end process;
| PROCESS_73 | ( clk0 ) |
count to generate write enable to the data path
Definition at line 843 of file ddr2_mem_ddr2_controller.vhd.
00843 process(clk0) 00844 begin 00845 if (clk0 = '1' and clk0'event) then 00846 if (rst = '1') then 00847 ctrl_WrEn_cnt(2 downto 0) <= "000"; 00848 elsif (wdf_rden_r = '1' or dummy_write_state_r = '1') then 00849 ctrl_WrEn_cnt(2 downto 0) <= burst_cnt(2 downto 0); 00850 elsif (ctrl_WrEn_cnt(2 downto 0) /= "000") then 00851 ctrl_WrEn_cnt(2 downto 0) <= ctrl_WrEn_cnt(2 downto 0)- "001"; 00852 else 00853 ctrl_WrEn_cnt(2 downto 0) <= "000"; 00854 end if; 00855 end if; 00856 end process;
| PROCESS_74 | ( ctrl_WrEn_cnt ) |
write enable to data path
Definition at line 859 of file ddr2_mem_ddr2_controller.vhd.
00859 process(ctrl_WrEn_cnt) 00860 begin 00861 if (ctrl_WrEn_cnt(2 downto 0) /= "000") then 00862 ctrl_write_en <= '1'; 00863 else 00864 ctrl_write_en <= '0'; 00865 end if; 00866 end process;
| PROCESS_75 | ( clk0 ) |
write enable to data path
Definition at line 870 of file ddr2_mem_ddr2_controller.vhd.
00870 process(clk0) 00871 begin 00872 00873 if (clk0 = '1' and clk0'event) then 00874 if (rst = '1') then 00875 ctrl_WrEn_r1 <= '0'; 00876 ctrl_write_en_r1 <= '0'; 00877 ctrl_write_en_r2 <= '0'; 00878 ctrl_write_en_r3 <= '0'; 00879 ctrl_write_en_r4 <= '0'; 00880 ctrl_write_en_r5 <= '0'; 00881 ctrl_write_en_r6 <= '0'; 00882 else 00883 ctrl_write_en_r1 <= ctrl_write_en; 00884 ctrl_write_en_r2 <= ctrl_write_en_r1; 00885 ctrl_write_en_r3 <= ctrl_write_en_r2; 00886 ctrl_write_en_r4 <= ctrl_write_en_r3; 00887 ctrl_write_en_r5 <= ctrl_write_en_r4; 00888 ctrl_write_en_r6 <= ctrl_write_en_r5; 00889 00890 case s1_h is 00891 when "0011" => ctrl_WrEn_r1 <= ctrl_write_en; 00892 when "0100" => ctrl_WrEn_r1 <= ctrl_write_en_r1; 00893 when "0101" => ctrl_WrEn_r1 <= ctrl_write_en_r2; 00894 when "0110" => ctrl_WrEn_r1 <= ctrl_write_en_r3; 00895 when "0111" => ctrl_WrEn_r1 <= ctrl_write_en_r4; 00896 when "1000" => ctrl_WrEn_r1 <= ctrl_write_en_r5; 00897 when "1001" => ctrl_WrEn_r1 <= ctrl_write_en_r6; 00898 when others => ctrl_WrEn_r1 <= '0'; 00899 end case; -- case(ADDITIVE_LATENCY_VALUE + CAS_LATENCY_VALUE ) 00900 00901 end if; 00902 end if; 00903 end process;
| PROCESS_76 | ( state , | |
| init_state ) |
reset DQS
Definition at line 906 of file ddr2_mem_ddr2_controller.vhd.
00906 process(state, init_state) 00907 begin 00908 if (state = FIRST_WRITE or init_state = INIT_PATTERN_WRITE) then 00909 dqs_reset <= '1'; 00910 else 00911 dqs_reset <= '0'; 00912 end if; 00913 end process;
| PROCESS_77 | ( clk0 ) |
DQS reset to data path.
Definition at line 918 of file ddr2_mem_ddr2_controller.vhd.
00918 process(clk0) 00919 begin 00920 00921 if (clk0 = '1' and clk0'event) then 00922 if (rst = '1') then 00923 ctrl_Dqs_Rst_r1 <= '0'; 00924 dqs_reset_r1 <= '0'; 00925 dqs_reset_r2 <= '0'; 00926 dqs_reset_r3 <= '0'; 00927 dqs_reset_r4 <= '0'; 00928 dqs_reset_r5 <= '0'; 00929 dqs_reset_r6 <= '0'; 00930 00931 else 00932 dqs_reset_r1 <= dqs_reset; 00933 dqs_reset_r2 <= dqs_reset_r1; 00934 dqs_reset_r3 <= dqs_reset_r2; 00935 dqs_reset_r4 <= dqs_reset_r3; 00936 dqs_reset_r5 <= dqs_reset_r4; 00937 dqs_reset_r6 <= dqs_reset_r5; 00938 00939 case s2_h is 00940 when "0011" => ctrl_Dqs_Rst_r1 <= dqs_reset; 00941 when "0100" => ctrl_Dqs_Rst_r1 <= dqs_reset_r1; 00942 when "0101" => ctrl_Dqs_Rst_r1 <= dqs_reset_r2; 00943 when "0110" => ctrl_Dqs_Rst_r1 <= dqs_reset_r3; 00944 when "0111" => ctrl_Dqs_Rst_r1 <= dqs_reset_r4; 00945 when "1000" => ctrl_Dqs_Rst_r1 <= dqs_reset_r5; 00946 when "1001" => ctrl_Dqs_Rst_r1 <= dqs_reset_r6; 00947 when others => ctrl_Dqs_Rst_r1 <= '0'; 00948 end case; -- case(ADDITIVE_LATENCY_VALUE + CAS_LATENCY_VALUE ) 00949 end if; 00950 end if; 00951 end process;
| PROCESS_78 | ( state , | |
| init_state , | ||
| wrburst_cnt ) |
enable DQS
Definition at line 954 of file ddr2_mem_ddr2_controller.vhd.
00954 process(state , init_state, wrburst_cnt) 00955 begin 00956 if ((state = FIRST_WRITE) or (state = BURST_WRITE) or (init_state = INIT_PATTERN_WRITE) or (wrburst_cnt /= "000")) then 00957 dqs_en <= '1'; 00958 else 00959 dqs_en <= '0'; 00960 end if; 00961 end process;
| PROCESS_79 | ( clk0 ) |
DQS enable to data path.
Definition at line 966 of file ddr2_mem_ddr2_controller.vhd.
00966 process(clk0) 00967 begin 00968 00969 if (clk0 = '1' and clk0'event) then 00970 if (rst = '1') then 00971 ctrl_Dqs_En_r1 <= '0'; 00972 dqs_en_r1 <= '0'; 00973 dqs_en_r2 <= '0'; 00974 dqs_en_r3 <= '0'; 00975 dqs_en_r4 <= '0'; 00976 dqs_en_r5 <= '0'; 00977 dqs_en_r6 <= '0'; 00978 00979 else 00980 dqs_en_r1 <= dqs_en; 00981 dqs_en_r2 <= dqs_en_r1; 00982 dqs_en_r3 <= dqs_en_r2; 00983 dqs_en_r4 <= dqs_en_r3; 00984 dqs_en_r5 <= dqs_en_r4; 00985 dqs_en_r6 <= dqs_en_r5; 00986 00987 case s3_h is 00988 when "0011" => ctrl_Dqs_En_r1 <= dqs_en; 00989 when "0100" => ctrl_Dqs_En_r1 <= dqs_en_r1; 00990 when "0101" => ctrl_Dqs_En_r1 <= dqs_en_r2; 00991 when "0110" => ctrl_Dqs_En_r1 <= dqs_en_r3; 00992 when "0111" => ctrl_Dqs_En_r1 <= dqs_en_r4; 00993 when "1000" => ctrl_Dqs_En_r1 <= dqs_en_r5; 00994 when "1001" => ctrl_Dqs_En_r1 <= dqs_en_r6; 00995 when others => ctrl_Dqs_En_r1 <= '0'; 00996 end case; 00997 end if; 00998 end if; 00999 end process;
| PROCESS_80 | ( clk0 ) |
cas count
Definition at line 1003 of file ddr2_mem_ddr2_controller.vhd.
01003 process(clk0) 01004 begin 01005 if (clk0 = '1' and clk0'event) then 01006 if (rst = '1') then 01007 cas_count(2 downto 0) <= "000"; 01008 elsif (init_state = INIT_DUMMY_FIRST_READ) then 01009 cas_count(2 downto 0) <= CAS_LATENCY_VALUE + ("00" & REGISTERED_VALUE); 01010 elsif (cas_count(2 downto 0) /= "000") then 01011 cas_count(2 downto 0) <= cas_count(2 downto 0) - "001"; 01012 else 01013 cas_count(2 downto 0) <= "000"; 01014 end if; 01015 end if; 01016 end process;
| PROCESS_81 | ( clk0 ) |
dummy_read enable
Definition at line 1019 of file ddr2_mem_ddr2_controller.vhd.
01019 process(clk0) 01020 begin 01021 if (clk0 = '1' and clk0'event) then 01022 if (rst = '1') then 01023 dummy_read_en <= '0'; 01024 elsif (init_state = INIT_DUMMY_READ) then 01025 dummy_read_en <= '1'; 01026 elsif (phy_Dly_Slct_Done = '1') then 01027 dummy_read_en <= '0'; 01028 else 01029 dummy_read_en <= dummy_read_en; 01030 end if; 01031 end if; 01032 end process;
| PROCESS_82 | ( clk0 ) |
ctrl_Dummyread_Start signal generation to the data path module
Definition at line 1035 of file ddr2_mem_ddr2_controller.vhd.
01035 process(clk0) 01036 begin 01037 if (clk0 = '1' and clk0'event) then 01038 if ((dummy_read_en = '1') and (cas_count = "000")) then 01039 ctrl_Dummyread_Start_r1 <= '1'; 01040 elsif (phy_Dly_Slct_Done = '1') then 01041 ctrl_Dummyread_Start_r1 <= '0'; 01042 else 01043 ctrl_Dummyread_Start_r1 <= ctrl_Dummyread_Start_r1; 01044 end if; 01045 end if; 01046 end process;
| PROCESS_83 | ( clk0 ) |
register ctrl_Dummyread_Start signal
Definition at line 1049 of file ddr2_mem_ddr2_controller.vhd.
01049 process(clk0) 01050 begin 01051 if (clk0 = '1' and clk0'event) then 01052 ctrl_Dummyread_Start_r2 <= ctrl_Dummyread_Start_r1; 01053 ctrl_Dummyread_Start_r3 <= ctrl_Dummyread_Start_r2; 01054 ctrl_Dummyread_Start_r4 <= ctrl_Dummyread_Start_r3; 01055 ctrl_Dummyread_Start <= ctrl_Dummyread_Start_r4; 01056 end if; 01057 end process;
| PROCESS_84 | ( clk0 ) |
read_wait/write_wait to idle count the state machine waits for 15 clock cycles in the write wait state for any wr/rd commands to be issued. If no commands are issued in 15 clock cycles, the statemachine issues enters the idle state and stays in the idle state until an auto refresh is required.
Definition at line 1063 of file ddr2_mem_ddr2_controller.vhd.
01063 process(clk0) 01064 begin 01065 if (clk0 = '1' and clk0'event) then 01066 if (rst = '1') then 01067 idle_cnt(3 downto 0) <= "0000"; 01068 elsif (state = FIRST_READ or state = FIRST_WRITE or state = BURST_READ or state = BURST_WRITE) then 01069 idle_cnt(3 downto 0) <= "1111"; 01070 elsif (idle_cnt(3 downto 0) /= "0000") then 01071 idle_cnt(3 downto 0) <= idle_cnt(3 downto 0) - "0001"; 01072 else 01073 idle_cnt(3 downto 0) <= "0000"; 01074 end if; 01075 end if; 01076 end process;
| PROCESS_85 | ( clk0 ) |
cas check
Definition at line 1079 of file ddr2_mem_ddr2_controller.vhd.
01079 process(clk0) 01080 begin 01081 if (clk0 = '1' and clk0'event) then 01082 if (rst = '1') then 01083 cas_check_count(3 downto 0) <= "0000"; 01084 elsif ((state_r2 = FIRST_READ) or (init_state_r2 = INIT_PATTERN_READ)) then 01085 cas_check_count(3 downto 0) <= (('0' & CAS_LATENCY_VALUE) - "0001"); 01086 elsif (cas_check_count(3 downto 0) /= "0000") then 01087 cas_check_count(3 downto 0) <= cas_check_count(3 downto 0) - "0001"; 01088 else 01089 cas_check_count(3 downto 0) <= "0000"; 01090 end if; 01091 end if; 01092 end process;
| PROCESS_86 | ( clk0 ) |
read burst count
Definition at line 1095 of file ddr2_mem_ddr2_controller.vhd.
01095 process(clk0) 01096 begin 01097 if (clk0 = '1' and clk0'event) then 01098 if (rst = '1') then 01099 rdburst_cnt(3 downto 0) <= "0000"; 01100 elsif (cas_check_count = "0010") then 01101 rdburst_cnt(3 downto 0) <= ('0' & burst_cnt(2 downto 0)); 01102 elsif(state_r3 = BURST_READ) then 01103 if(burst_cnt(2) = '1') then 01104 rdburst_cnt(3 downto 0) <= ((burst_cnt(2 downto 0) & '0') -("0111" - ('0' & CAS_LATENCY_VALUE))); 01105 else 01106 rdburst_cnt(3 downto 0) <= ((burst_cnt(2 downto 0) & '0') -("0101" - ('0' & CAS_LATENCY_VALUE))); 01107 end if; 01108 elsif (rdburst_cnt(3 downto 0) /= "0000") then 01109 rdburst_cnt(3 downto 0) <= rdburst_cnt(3 downto 0) - "0001"; 01110 else 01111 rdburst_cnt(3 downto 0) <= "0000"; 01112 end if; 01113 end if; 01114 end process;
| PROCESS_87 | ( rdburst_cnt ) |
read enable to data path
Definition at line 1117 of file ddr2_mem_ddr2_controller.vhd.
01117 process(rdburst_cnt) 01118 begin 01119 if (rdburst_cnt = "0000") then 01120 ctrl_read_en <= '0'; 01121 else 01122 ctrl_read_en <= '1'; 01123 end if; 01124 end process;
| PROCESS_88 | ( clk0 ) |
read enable to data path
Definition at line 1127 of file ddr2_mem_ddr2_controller.vhd.
01127 process(clk0) 01128 begin 01129 if (clk0 = '1' and clk0'event) then 01130 if (rst = '1') then 01131 ctrl_read_en_r <= '0'; 01132 ctrl_read_en_r1 <= '0'; 01133 ctrl_read_en_r2 <= '0'; 01134 ctrl_read_en_r3 <= '0'; 01135 else 01136 ctrl_read_en_r <= ctrl_read_en; 01137 ctrl_read_en_r1 <= ctrl_read_en_r; 01138 ctrl_read_en_r2 <= ctrl_read_en_r1; 01139 ctrl_read_en_r3 <= ctrl_read_en_r2; 01140 end if; 01141 end if; 01142 end process;
| PROCESS_89 | ( clk0 ) |
read enable to data path
Definition at line 1147 of file ddr2_mem_ddr2_controller.vhd.
01147 process(clk0) 01148 begin 01149 01150 if (clk0 = '1' and clk0'event) then 01151 if (rst = '1') then 01152 ctrl_RdEn_r1 <= '0'; 01153 else 01154 case s4_h is 01155 when "000" => ctrl_RdEn_r1 <= ctrl_read_en; 01156 when "001" => ctrl_RdEn_r1 <= ctrl_read_en_r; 01157 when "010" => ctrl_RdEn_r1 <= ctrl_read_en_r1; 01158 when "011" => ctrl_RdEn_r1 <= ctrl_read_en_r2; 01159 when "100" => ctrl_RdEn_r1 <= ctrl_read_en_r3; 01160 when others => ctrl_RdEn_r1 <= '0'; 01161 end case; -- case(ADDITIVE_LATENCY_VALUE) 01162 end if; -- else: !if(rst) 01163 end if; 01164 end process;
| PROCESS_90 | ( clk0 ) |
write address FIFO read enable signals
write data fifo read enable
Definition at line 1175 of file ddr2_mem_ddr2_controller.vhd.
01175 process(clk0) 01176 begin 01177 if (clk0 = '1' and clk0'event) then 01178 if (rst = '1') then 01179 wdf_rden_r <= '0'; 01180 elsif ((state = FIRST_WRITE) or (state = BURST_WRITE) or (init_state = INIT_PATTERN_WRITE)) then -- place holder for BURST_WRITE 01181 wdf_rden_r <= '1'; 01182 else 01183 wdf_rden_r <= '0'; 01184 end if; 01185 end if; 01186 end process;
| PROCESS_91 | ( clk0 ) |
write data fifo read enable
Definition at line 1189 of file ddr2_mem_ddr2_controller.vhd.
01189 process(clk0) 01190 begin 01191 if (clk0 = '1' and clk0'event) then 01192 if (rst = '1') then 01193 wdf_rden_r2 <= '0'; 01194 wdf_rden_r3 <= '0'; 01195 wdf_rden_r4 <= '0'; 01196 else 01197 wdf_rden_r2 <= wdf_rden_r; 01198 wdf_rden_r3 <= wdf_rden_r2; 01199 wdf_rden_r4 <= wdf_rden_r3; 01200 end if; --else: !if(rst) 01201 end if; 01202 end process;
| PROCESS_92 | ( burst_cnt , | |
| wdf_rden_r , | ||
| wdf_rden_r2 , | ||
| wdf_rden_r3 , | ||
| wdf_rden_r4 ) |
Read enable to the data fifo.
Definition at line 1205 of file ddr2_mem_ddr2_controller.vhd.
01205 process(burst_cnt, wdf_rden_r, wdf_rden_r2, wdf_rden_r3, wdf_rden_r4) 01206 begin 01207 if (burst_cnt = "010") then 01208 ctrl_wdf_read_en <= (wdf_rden_r or wdf_rden_r2); 01209 elsif (burst_cnt = "100") then 01210 ctrl_wdf_read_en <= (wdf_rden_r or wdf_rden_r2 or wdf_rden_r3 or wdf_rden_r4); 01211 else 01212 ctrl_wdf_read_en <= '0'; 01213 end if; 01214 end process;
| PROCESS_93 | ( clk0 ) |
Read enable to the data fifo.
Definition at line 1219 of file ddr2_mem_ddr2_controller.vhd.
01219 process(clk0) 01220 begin 01221 if (clk0 = '1' and clk0'event) then 01222 if (rst = '1') then 01223 ctrl_Wdf_RdEn_int <= '0'; 01224 ctrl_wdf_read_en_r1 <= '0'; 01225 ctrl_wdf_read_en_r2 <= '0'; 01226 ctrl_wdf_read_en_r3 <= '0'; 01227 ctrl_wdf_read_en_r4 <= '0'; 01228 ctrl_wdf_read_en_r5 <= '0'; 01229 ctrl_wdf_read_en_r6 <= '0'; 01230 else 01231 ctrl_wdf_read_en_r1 <= ctrl_wdf_read_en; 01232 ctrl_wdf_read_en_r2 <= ctrl_wdf_read_en_r1; 01233 ctrl_wdf_read_en_r3 <= ctrl_wdf_read_en_r2; 01234 ctrl_wdf_read_en_r4 <= ctrl_wdf_read_en_r3; 01235 ctrl_wdf_read_en_r5 <= ctrl_wdf_read_en_r4; 01236 ctrl_wdf_read_en_r6 <= ctrl_wdf_read_en_r5; 01237 case s5_h is 01238 when "0011" => ctrl_Wdf_RdEn_int <= ctrl_wdf_read_en; 01239 when "0100" => ctrl_Wdf_RdEn_int <= ctrl_wdf_read_en_r1; 01240 when "0101" => ctrl_Wdf_RdEn_int <= ctrl_wdf_read_en_r2; 01241 when "0110" => ctrl_Wdf_RdEn_int <= ctrl_wdf_read_en_r3; 01242 when "0111" => ctrl_Wdf_RdEn_int <= ctrl_wdf_read_en_r4; 01243 when "1000" => ctrl_Wdf_RdEn_int <= ctrl_wdf_read_en_r5; 01244 when "1001" => ctrl_Wdf_RdEn_int <= ctrl_wdf_read_en_r6; 01245 when others => ctrl_Wdf_RdEn_int <= '0'; 01246 end case; 01247 end if; -- else: !if(rst) 01248 end if; 01249 end process;
| PROCESS_94 | ( clk0 ) |
hold init for a while
Definition at line 1252 of file ddr2_mem_ddr2_controller.vhd.
01252 process(clk0) 01253 begin 01254 if (clk0 = '1' and clk0'event) then 01255 if (rst = '1') then 01256 count6 <= "000000"; 01257 else 01258 case init_state is 01259 01260 when INIT_PRECHARGE_WAIT | INIT_MODE_REGISTER_WAIT | INIT_AUTO_REFRESH_WAIT | 01261 INIT_ACTIVE_WAIT | INIT_PATTERN_WRITE_READ | INIT_PATTERN_READ_WAIT | 01262 INIT_DUMMY_READ_WAIT | INIT_DUMMY_ACTIVE_WAIT => 01263 count6 <= count6 + "000001"; 01264 01265 when others => count6 <= "000000"; 01266 end case; 01267 end if; 01268 end if; 01269 end process;
| PROCESS_95 | ( clk0 ) |
initialize FSM
Definition at line 1272 of file ddr2_mem_ddr2_controller.vhd.
01272 process(clk0) 01273 begin 01274 if (clk0 = '1' and clk0'event) then 01275 if (rst = '1') then 01276 init_state <= INIT_IDLE; 01277 else 01278 init_state <= init_next_state; 01279 end if; 01280 end if; 01281 end process;
| PROCESS_96 | ( clk0 ) |
| PROCESS_97 | ( clk0 ) |
dummy write flag FF
Definition at line 1296 of file ddr2_mem_ddr2_controller.vhd.
01296 process(clk0) 01297 begin 01298 if (clk0 = '1' and clk0'event) then 01299 if (rst = '1') then 01300 dummy_write_flag_r <= '0'; 01301 elsif(phy_Dly_Slct_Done = '1' and COMP_DONE_r = '0') then 01302 dummy_write_flag_r <= '1'; 01303 elsif(COMP_DONE_r = '1') then 01304 dummy_write_flag_r <= '0'; 01305 end if; 01306 end if; 01307 end process;
| PROCESS_98 | ( clk0 ) |
init dummy write state
Definition at line 1312 of file ddr2_mem_ddr2_controller.vhd.
01312 process(clk0) 01313 begin 01314 if (clk0 = '1' and clk0'event) then 01315 if (rst = '1') then 01316 dummy_write_state_r <= '0'; 01317 else 01318 dummy_write_state_r <= dummy_write_state; 01319 end if; 01320 end if; 01321 end process;
| PROCESS_99 | ( RD , | |
| RD_r , | ||
| WR , | ||
| WR_r , | ||
| LMR_r , | ||
| PRE_r , | ||
| ACT_r , | ||
| REF_r , | ||
| auto_ref , | ||
| chip_cnt , | ||
| auto_cnt , | ||
| conflict_detect , | ||
| conflict_detect_r , | ||
| conflict_resolved_r , | ||
| count_200cycle_done_r , | ||
| idle_cnt , | ||
| init_count , | ||
| init_memory , | ||
| mrd_count , | ||
| LMR_PRE_REF_ACT_cmd_r , | ||
| phy_Dly_Slct_Done , | ||
| ras_count , | ||
| rcd_count , | ||
| rd_to_wr_count , | ||
| read_burst_cnt , | ||
| rfc_count , | ||
| rp_count , | ||
| rtp_count , | ||
| init_state , | ||
| wr_to_rd_count , | ||
| wrburst_cnt , | ||
| wtp_count , | ||
| done_200us , | ||
| cs_width0 , | ||
| dummy_write_flag_r , | ||
| COMP_DONE_r , | ||
| count6 ) |
init state machine
Definition at line 1329 of file ddr2_mem_ddr2_controller.vhd.
01329 process(RD, RD_r, WR, WR_r, LMR_r, PRE_r, ACT_r, REF_r, 01330 auto_ref, chip_cnt, auto_cnt, conflict_detect, conflict_detect_r, 01331 conflict_resolved_r, count_200cycle_done_r, idle_cnt, 01332 init_count, init_memory, mrd_count, LMR_PRE_REF_ACT_cmd_r, 01333 phy_Dly_Slct_Done, ras_count, rcd_count, rd_to_wr_count, 01334 read_burst_cnt, rfc_count, rp_count, rtp_count, 01335 init_state, wr_to_rd_count, wrburst_cnt, wtp_count, done_200us, 01336 cs_width0, dummy_write_flag_r, COMP_DONE_r, count6) 01337 begin 01338 init_next_state <= init_state; 01339 case init_state is 01340 when INIT_IDLE => 01341 if (init_memory = '1' and done_200us = '1') then 01342 case init_count is -- synthesis parallel_case full_case 01343 when "0000" => 01344 init_next_state <= INIT_COUNT_200; 01345 01346 when "0001" => 01347 if (count_200cycle_done_r = '1') then 01348 init_next_state <= INIT_PRECHARGE; 01349 else 01350 init_next_state <= INIT_IDLE; 01351 end if; 01352 01353 when "0010" => 01354 init_next_state <= INIT_LOAD_MODE; -- emr(2) 01355 01356 when "0011" => 01357 init_next_state <= INIT_LOAD_MODE; -- emr(3) 01358 01359 when "0100" => 01360 init_next_state <= INIT_LOAD_MODE; -- emr 01361 01362 when "0101" => 01363 init_next_state <= INIT_LOAD_MODE; --lmr 01364 01365 when "0110" => 01366 init_next_state <= INIT_PRECHARGE; 01367 01368 when "0111" => 01369 init_next_state <= INIT_AUTO_REFRESH; 01370 01371 when "1000" => 01372 init_next_state <= INIT_AUTO_REFRESH; 01373 01374 when "1001" => 01375 init_next_state <= INIT_LOAD_MODE; 01376 01377 when "1010" => -- EMR OCD DEFAULT 01378 init_next_state <= INIT_LOAD_MODE; 01379 01380 when "1011" => -- EMR OCD EXIT 01381 init_next_state <= INIT_LOAD_MODE; 01382 01383 when "1100" => 01384 init_next_state <= INIT_COUNT_200; 01385 01386 when "1101" => 01387 if (chip_cnt < cs_width0) then 01388 -- if (chip_cnt < (cs_width- 1)) then 01389 init_next_state <= INIT_DEEP_MEMORY_ST; 01390 elsif (Phy_Mode = '1' and count_200cycle_done_r = '1') then 01391 init_next_state <= INIT_DUMMY_READ_CYCLES; 01392 else 01393 init_next_state <= INIT_IDLE; 01394 end if; 01395 01396 when "1110" => 01397 if (phy_Dly_Slct_Done = '1') then 01398 init_next_state <= INIT_PRECHARGE; 01399 else 01400 init_next_state <= INIT_IDLE; 01401 end if; 01402 01403 when "1111" => 01404 if (COMP_DONE_r = '1') then 01405 init_next_state <= INIT_IDLE; 01406 end if; 01407 01408 when others => init_next_state <= INIT_IDLE; 01409 01410 end case; -- case(init_count) 01411 01412 end if; -- case: INIT_IDLE 01413 01414 when INIT_DEEP_MEMORY_ST => 01415 init_next_state <= INIT_IDLE; 01416 01417 when INIT_COUNT_200 => 01418 init_next_state <= INIT_COUNT_200_WAIT; 01419 01420 when INIT_COUNT_200_WAIT => 01421 if (count_200cycle_done_r = '1') then 01422 init_next_state <= INIT_IDLE; 01423 else 01424 init_next_state <= INIT_COUNT_200_WAIT; 01425 end if; 01426 01427 when INIT_DUMMY_READ_CYCLES => 01428 init_next_state <= INIT_DUMMY_ACTIVE; 01429 01430 when INIT_DUMMY_ACTIVE => 01431 init_next_state <= INIT_DUMMY_ACTIVE_WAIT; 01432 01433 when INIT_DUMMY_ACTIVE_WAIT => 01434 if (count6 = cntnext) then 01435 init_next_state <= INIT_DUMMY_FIRST_READ; 01436 else 01437 init_next_state <= INIT_DUMMY_ACTIVE_WAIT; 01438 end if; 01439 01440 when INIT_DUMMY_FIRST_READ => 01441 init_next_state <= INIT_DUMMY_READ_WAIT; 01442 01443 when INIT_DUMMY_READ => 01444 init_next_state <= INIT_DUMMY_READ_WAIT; 01445 01446 when INIT_DUMMY_READ_WAIT => 01447 if (phy_Dly_Slct_Done = '1') then 01448 if(count6 = cntnext) then 01449 init_next_state <= INIT_PATTERN_WRITE; 01450 else 01451 init_next_state <= INIT_DUMMY_READ_WAIT; 01452 end if; 01453 else 01454 init_next_state <= INIT_DUMMY_READ; 01455 end if; 01456 01457 -- pattern write 01458 when INIT_PRECHARGE => 01459 init_next_state <= INIT_PRECHARGE_WAIT; 01460 01461 when INIT_PRECHARGE_WAIT => 01462 if (count6 = cntnext) then 01463 init_next_state <= INIT_IDLE; 01464 else 01465 init_next_state <= INIT_PRECHARGE_WAIT; 01466 end if; 01467 01468 when INIT_LOAD_MODE => 01469 init_next_state <= INIT_MODE_REGISTER_WAIT; 01470 01471 when INIT_MODE_REGISTER_WAIT => 01472 if (count6 = cntnext) then 01473 init_next_state <= INIT_IDLE; 01474 else 01475 init_next_state <= INIT_MODE_REGISTER_WAIT; 01476 end if; 01477 01478 when INIT_AUTO_REFRESH => 01479 init_next_state <= INIT_AUTO_REFRESH_WAIT; 01480 01481 when INIT_AUTO_REFRESH_WAIT => 01482 if (count6 = cntnext) then 01483 init_next_state <= INIT_IDLE; 01484 else 01485 init_next_state <= INIT_AUTO_REFRESH_WAIT; 01486 end if; 01487 01488 when INIT_ACTIVE => 01489 init_next_state <= INIT_ACTIVE_WAIT; 01490 01491 when INIT_ACTIVE_WAIT => -- first active or when a new row is opened 01492 if (count6 = cntnext) then 01493 init_next_state <= INIT_IDLE; 01494 else 01495 init_next_state <= INIT_ACTIVE_WAIT; 01496 end if; 01497 01498 when INIT_PATTERN_WRITE => 01499 init_next_state <= INIT_PATTERN_WRITE_READ; 01500 01501 when INIT_PATTERN_WRITE_READ => 01502 if (count6 = cntnext) then 01503 init_next_state <= INIT_PATTERN_READ; 01504 else 01505 init_next_state <= INIT_PATTERN_WRITE_READ; 01506 end if; 01507 01508 when INIT_PATTERN_READ => 01509 init_next_state <= INIT_PATTERN_READ_WAIT; 01510 01511 when INIT_PATTERN_READ_WAIT => 01512 if (COMP_DONE_r = '1') then 01513 init_next_state <= INIT_PRECHARGE; -- Precharge fix after pattern read 01514 else 01515 init_next_state <= INIT_PATTERN_READ_WAIT; 01516 end if; 01517 01518 when others => init_next_state <= INIT_IDLE; 01519 01520 end case; 01521 end process;
The documentation for this class was generated from the following file:
