clock_divider Entity Reference
Prescaler. More...
Inheritance diagram for clock_divider:
Collaboration diagram for clock_divider:
Architectures | |
| clock_divider_arc | Architecture |
| Prescaler. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
Generics | |
| DIVISION_FACTOR | integer range 0 to 127 := 2 |
| only even numbers | |
| INITIAL_VALUE | integer range 0 to 127 := 2 |
| only even numbers | |
Ports | |
| CLK_IN | in std_logic |
| Clock In. | |
| CLK_OUT | out std_logic |
| Clock Out. | |
Detailed Description
Prescaler.Definition at line 33 of file clock_divider.vhd.
Member Data Documentation
CLK_IN in std_logic [Port] |
CLK_OUT out std_logic [Port] |
DIVISION_FACTOR integer range 0 to 127 := 2 [Generic] |
ieee library [Library] |
INITIAL_VALUE integer range 0 to 127 := 2 [Generic] |
std_logic_1164 package [Package] |
std_logic_arith package [Package] |
arithmetic operations on std_logic datatypes, see file
Definition at line 28 of file clock_divider.vhd.
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 30 of file clock_divider.vhd.
The documentation for this class was generated from the following file:
