rios_all Entity Reference
Combination of RocketIOs for each side of the IP. More...
Inheritance diagram for rios_all:
Collaboration diagram for rios_all:
Architectures | |
| rios_all_arc | Architecture |
| Combination of RocketIOs for each side of the IP. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
| work | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
| main_components | Package <main_components> |
Ports | |
| BCLK | in std_logic |
| Bunch Clock. | |
| BCLK4X | in std_logic |
| BC x4. | |
| RIOCLK_1 | in std_logic |
| BC x4 from RocketIO clock-module. | |
| RIOCLK_2 | in std_logic |
| BC x4 from RocketIO clock-module. | |
| BCLK2X | in std_logic |
| BC x2. | |
| EN | in std_logic |
| Enable to sync edge detection. | |
| RESET | in std_logic |
| Reset. | |
| SEP_RESET | in std_logic_vector ( 7 downto 0 ) |
| Reset for single channels. | |
| CALIBRATE_RIOS | in std_logic |
| enable calibration procedure, deassert once CAL_DONE = 1 | |
| LOCK_OUT | out std_logic |
| global PLL lock flag | |
| RIOS_READY | out std_logic |
| global RIO init done flag | |
| DONE | out std_logic |
| global RIO calibration done flag | |
| CHECK | out std_logic |
| global RIO calibration check flag | |
| RXN_C_IE | in std_logic_vector ( 1 downto 0 ) |
| serial rx data in | |
| RXP_C_IE | in std_logic_vector ( 1 downto 0 ) |
| serial rx data in | |
| TXN_C_IE | out std_logic_vector ( 1 downto 0 ) |
| serial tx data out | |
| TXP_C_IE | out std_logic_vector ( 1 downto 0 ) |
| serial tx data out | |
| RXN_C_AH | in std_logic_vector ( 1 downto 0 ) |
| serial rx data in | |
| RXP_C_AH | in std_logic_vector ( 1 downto 0 ) |
| serial rx data in | |
| TXN_C_AH | out std_logic_vector ( 1 downto 0 ) |
| serial tx data out | |
| TXP_C_AH | out std_logic_vector ( 1 downto 0 ) |
| serial tx data out | |
| RXN_A_WM | in std_logic_vector ( 1 downto 0 ) |
| serial rx data in | |
| RXP_A_WM | in std_logic_vector ( 1 downto 0 ) |
| serial rx data in | |
| TXN_A_WM | out std_logic_vector ( 1 downto 0 ) |
| serial tx data out | |
| TXP_A_WM | out std_logic_vector ( 1 downto 0 ) |
| serial tx data out | |
| RXN_A_HH | in std_logic_vector ( 1 downto 0 ) |
| serial rx data in | |
| RXP_A_HH | in std_logic_vector ( 1 downto 0 ) |
| serial rx data in | |
| TXN_A_HH | out std_logic_vector ( 1 downto 0 ) |
| serial tx data out | |
| TXP_A_HH | out std_logic_vector ( 1 downto 0 ) |
| serial tx data out | |
| CAL_IRENA | in std_logic |
| recalibrate 1 ch after trip | |
| CAL_EWA | in std_logic |
| recalibrate 1 ch after trip | |
| CAL_ANDREJ | in std_logic |
| recalibrate 1 ch after trip | |
| CAL_HEINZ | in std_logic |
| recalibrate 1 ch after trip | |
| CAL_MARKO | in std_logic |
| recalibrate 1 ch after trip | |
| CAL_WILLIAM | in std_logic |
| recalibrate 1 ch after trip | |
| CAL_HARRIS | in std_logic |
| recalibrate 1 ch after trip | |
| CAL_HELMUT | in std_logic |
| recalibrate 1 ch after trip | |
| MASK_IRENA | out std_logic |
| data mask 1ch | |
| MASK_EWA | out std_logic |
| data mask 1ch | |
| MASK_ANDREJ | out std_logic |
| data mask 1ch | |
| MASK_HEINZ | out std_logic |
| data mask 1ch | |
| MASK_MARKO | out std_logic |
| data mask 1ch | |
| MASK_WILLIAM | out std_logic |
| data mask 1ch | |
| MASK_HARRIS | out std_logic |
| data mask 1ch | |
| MASK_HELMUT | out std_logic |
| data mask 1ch | |
| RX_LOCK1 | out std_logic |
| RX lock flag 1ch. | |
| RX_LOCK2 | out std_logic |
| RX lock flag 1ch. | |
| RX_LOCK3 | out std_logic |
| RX lock flag 1ch. | |
| RX_LOCK4 | out std_logic |
| RX lock flag 1ch. | |
| RX_LOCK5 | out std_logic |
| RX lock flag 1ch. | |
| RX_LOCK6 | out std_logic |
| RX lock flag 1ch. | |
| RX_LOCK7 | out std_logic |
| RX lock flag 1ch. | |
| RX_LOCK8 | out std_logic |
| RX lock flag 1ch. | |
| TX_LOCK1 | out std_logic |
| TX lock flag 1ch. | |
| TX_LOCK2 | out std_logic |
| TX lock flag 1ch. | |
| TX_LOCK3 | out std_logic |
| TX lock flag 1ch. | |
| TX_LOCK4 | out std_logic |
| TX lock flag 1ch. | |
| TX_LOCK5 | out std_logic |
| TX lock flag 1ch. | |
| TX_LOCK6 | out std_logic |
| TX lock flag 1ch. | |
| TX_LOCK7 | out std_logic |
| TX lock flag 1ch. | |
| TX_LOCK8 | out std_logic |
| TX lock flag 1ch. | |
| RX_READY1 | out std_logic |
| RX ready flag 1ch. | |
| RX_READY2 | out std_logic |
| RX ready flag 1ch. | |
| RX_READY3 | out std_logic |
| RX ready flag 1ch. | |
| RX_READY4 | out std_logic |
| RX ready flag 1ch. | |
| RX_READY5 | out std_logic |
| RX ready flag 1ch. | |
| RX_READY6 | out std_logic |
| RX ready flag 1ch. | |
| RX_READY7 | out std_logic |
| RX ready flag 1ch. | |
| RX_READY8 | out std_logic |
| RX ready flag 1ch. | |
| TX_READY1 | out std_logic |
| TX ready flag 1ch. | |
| TX_READY2 | out std_logic |
| TX ready flag 1ch. | |
| TX_READY3 | out std_logic |
| TX ready flag 1ch. | |
| TX_READY4 | out std_logic |
| TX ready flag 1ch. | |
| TX_READY5 | out std_logic |
| TX ready flag 1ch. | |
| TX_READY6 | out std_logic |
| TX ready flag 1ch. | |
| TX_READY7 | out std_logic |
| TX ready flag 1ch. | |
| TX_READY8 | out std_logic |
| TX ready flag 1ch. | |
| MULT_IRENA | out std_logic_vector ( 7 downto 0 ) |
| multiplicity 1ch | |
| MULT_EWA | out std_logic_vector ( 7 downto 0 ) |
| multiplicity 1ch | |
| MULT_ANDREJ | out std_logic_vector ( 7 downto 0 ) |
| multiplicity 1ch | |
| MULT_HEINZ | out std_logic_vector ( 7 downto 0 ) |
| multiplicity 1ch | |
| MULT_MARKO | out std_logic_vector ( 7 downto 0 ) |
| multiplicity 1ch | |
| MULT_WILLIAM | out std_logic_vector ( 7 downto 0 ) |
| multiplicity 1ch | |
| MULT_HARRIS | out std_logic_vector ( 7 downto 0 ) |
| multiplicity 1ch | |
| MULT_HELMUT | out std_logic_vector ( 7 downto 0 ) |
| multiplicity 1ch | |
| PROC_DATA | out std_logic_vector ( 191 downto 0 ) |
| processed data | |
| RAW_DATA | out std_logic_vector ( 255 downto 0 ) |
| raw data | |
| ADJUST_TIME_IRENA | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_EWA | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_ANDREJ | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_HEINZ | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_MARKO | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_WILLIAM | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_HARRIS | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_HELMUT | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_IRENA2 | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_EWA2 | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_ANDREJ2 | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_HEINZ2 | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_MARKO2 | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_WILLIAM2 | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_HARRIS2 | in integer range 0 to 32 |
| fine delay 1ch | |
| ADJUST_TIME_HELMUT2 | in integer range 0 to 32 |
| fine delay 1ch | |
| COARSE_TIME_IRENA | in std_logic_vector ( 7 downto 0 ) |
| coarse delay 1ch | |
| COARSE_TIME_EWA | in std_logic_vector ( 7 downto 0 ) |
| coarse delay 1ch | |
| COARSE_TIME_ANDREJ | in std_logic_vector ( 7 downto 0 ) |
| coarse delay 1ch | |
| COARSE_TIME_HEINZ | in std_logic_vector ( 7 downto 0 ) |
| coarse delay 1ch | |
| COARSE_TIME_MARKO | in std_logic_vector ( 7 downto 0 ) |
| coarse delay 1ch | |
| COARSE_TIME_WILLIAM | in std_logic_vector ( 7 downto 0 ) |
| coarse delay 1ch | |
| COARSE_TIME_HARRIS | in std_logic_vector ( 7 downto 0 ) |
| coarse delay 1ch | |
| COARSE_TIME_HELMUT | in std_logic_vector ( 7 downto 0 ) |
| coarse delay 1ch | |
Detailed Description
Combination of RocketIOs for each side of the IP.Definition at line 40 of file rios_all.vhd.
Member Data Documentation
ADJUST_TIME_ANDREJ in integer range 0 to 32 [Port] |
ADJUST_TIME_ANDREJ2 in integer range 0 to 32 [Port] |
ADJUST_TIME_EWA in integer range 0 to 32 [Port] |
ADJUST_TIME_EWA2 in integer range 0 to 32 [Port] |
ADJUST_TIME_HARRIS in integer range 0 to 32 [Port] |
ADJUST_TIME_HARRIS2 in integer range 0 to 32 [Port] |
ADJUST_TIME_HEINZ in integer range 0 to 32 [Port] |
ADJUST_TIME_HEINZ2 in integer range 0 to 32 [Port] |
ADJUST_TIME_HELMUT in integer range 0 to 32 [Port] |
ADJUST_TIME_HELMUT2 in integer range 0 to 32 [Port] |
ADJUST_TIME_IRENA in integer range 0 to 32 [Port] |
ADJUST_TIME_IRENA2 in integer range 0 to 32 [Port] |
ADJUST_TIME_MARKO in integer range 0 to 32 [Port] |
ADJUST_TIME_MARKO2 in integer range 0 to 32 [Port] |
ADJUST_TIME_WILLIAM in integer range 0 to 32 [Port] |
ADJUST_TIME_WILLIAM2 in integer range 0 to 32 [Port] |
BCLK in std_logic [Port] |
BCLK2X in std_logic [Port] |
BCLK4X in std_logic [Port] |
CAL_ANDREJ in std_logic [Port] |
CAL_EWA in std_logic [Port] |
CAL_HARRIS in std_logic [Port] |
CAL_HEINZ in std_logic [Port] |
CAL_HELMUT in std_logic [Port] |
CAL_IRENA in std_logic [Port] |
CAL_MARKO in std_logic [Port] |
CAL_WILLIAM in std_logic [Port] |
CALIBRATE_RIOS in std_logic [Port] |
enable calibration procedure, deassert once CAL_DONE = 1
Definition at line 50 of file rios_all.vhd.
CHECK out std_logic [Port] |
COARSE_TIME_ANDREJ in std_logic_vector ( 7 downto 0 ) [Port] |
COARSE_TIME_EWA in std_logic_vector ( 7 downto 0 ) [Port] |
COARSE_TIME_HARRIS in std_logic_vector ( 7 downto 0 ) [Port] |
COARSE_TIME_HEINZ in std_logic_vector ( 7 downto 0 ) [Port] |
COARSE_TIME_HELMUT in std_logic_vector ( 7 downto 0 ) [Port] |
COARSE_TIME_IRENA in std_logic_vector ( 7 downto 0 ) [Port] |
COARSE_TIME_MARKO in std_logic_vector ( 7 downto 0 ) [Port] |
COARSE_TIME_WILLIAM in std_logic_vector ( 7 downto 0 ) [Port] |
DONE out std_logic [Port] |
EN in std_logic [Port] |
ieee library [Library] |
LOCK_OUT out std_logic [Port] |
MASK_ANDREJ out std_logic [Port] |
MASK_EWA out std_logic [Port] |
MASK_HARRIS out std_logic [Port] |
MASK_HEINZ out std_logic [Port] |
MASK_HELMUT out std_logic [Port] |
MASK_IRENA out std_logic [Port] |
MASK_MARKO out std_logic [Port] |
MASK_WILLIAM out std_logic [Port] |
MULT_ANDREJ out std_logic_vector ( 7 downto 0 ) [Port] |
MULT_EWA out std_logic_vector ( 7 downto 0 ) [Port] |
MULT_HARRIS out std_logic_vector ( 7 downto 0 ) [Port] |
MULT_HEINZ out std_logic_vector ( 7 downto 0 ) [Port] |
MULT_HELMUT out std_logic_vector ( 7 downto 0 ) [Port] |
MULT_IRENA out std_logic_vector ( 7 downto 0 ) [Port] |
MULT_MARKO out std_logic_vector ( 7 downto 0 ) [Port] |
MULT_WILLIAM out std_logic_vector ( 7 downto 0 ) [Port] |
PROC_DATA out std_logic_vector ( 191 downto 0 ) [Port] |
RAW_DATA out std_logic_vector ( 255 downto 0 ) [Port] |
RESET in std_logic [Port] |
RIOCLK_1 in std_logic [Port] |
RIOCLK_2 in std_logic [Port] |
RIOS_READY out std_logic [Port] |
RX_LOCK1 out std_logic [Port] |
RX_LOCK2 out std_logic [Port] |
RX_LOCK3 out std_logic [Port] |
RX_LOCK4 out std_logic [Port] |
RX_LOCK5 out std_logic [Port] |
RX_LOCK6 out std_logic [Port] |
RX_LOCK7 out std_logic [Port] |
RX_LOCK8 out std_logic [Port] |
RX_READY1 out std_logic [Port] |
RX_READY2 out std_logic [Port] |
RX_READY3 out std_logic [Port] |
RX_READY4 out std_logic [Port] |
RX_READY5 out std_logic [Port] |
RX_READY6 out std_logic [Port] |
RX_READY7 out std_logic [Port] |
RX_READY8 out std_logic [Port] |
RXN_A_HH in std_logic_vector ( 1 downto 0 ) [Port] |
RXN_A_WM in std_logic_vector ( 1 downto 0 ) [Port] |
RXN_C_AH in std_logic_vector ( 1 downto 0 ) [Port] |
RXN_C_IE in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_A_HH in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_A_WM in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_C_AH in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_C_IE in std_logic_vector ( 1 downto 0 ) [Port] |
SEP_RESET in std_logic_vector ( 7 downto 0 ) [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 27 of file rios_all.vhd.
std_logic_arith package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 31 of file rios_all.vhd.
TX_LOCK1 out std_logic [Port] |
TX_LOCK2 out std_logic [Port] |
TX_LOCK3 out std_logic [Port] |
TX_LOCK4 out std_logic [Port] |
TX_LOCK5 out std_logic [Port] |
TX_LOCK6 out std_logic [Port] |
TX_LOCK7 out std_logic [Port] |
TX_LOCK8 out std_logic [Port] |
TX_READY1 out std_logic [Port] |
TX_READY2 out std_logic [Port] |
TX_READY3 out std_logic [Port] |
TX_READY4 out std_logic [Port] |
TX_READY5 out std_logic [Port] |
TX_READY6 out std_logic [Port] |
TX_READY7 out std_logic [Port] |
TX_READY8 out std_logic [Port] |
TXN_A_HH out std_logic_vector ( 1 downto 0 ) [Port] |
TXN_A_WM out std_logic_vector ( 1 downto 0 ) [Port] |
TXN_C_AH out std_logic_vector ( 1 downto 0 ) [Port] |
TXN_C_IE out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_A_HH out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_A_WM out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_C_AH out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_C_IE out std_logic_vector ( 1 downto 0 ) [Port] |
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
