bcm_aaa Entity Reference
top module of BCM AAA design More...
Inheritance diagram for bcm_aaa:
Collaboration diagram for bcm_aaa:
Architectures | |
| bcm_aaa_arc | Architecture |
| top module of BCM AAA design More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
| work | |
| Library with project specific headers. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions & operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions & operators for signed & unsigned datatypes, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
| main_components | Package <main_components> |
| Header with declarations of main design components. | |
| build_parameters | Package <build_parameters> |
| Header with config parameters for building the project. | |
Ports | |
| SYSCLK | in std_logic |
| 100 MHz from ML410 | |
| UPPER_MGTCLK_PAD_P_IN_EX | in std_logic_vector ( 1 downto 0 ) |
| RIO refclks, positive. | |
| UPPER_MGTCLK_PAD_N_IN_EX | in std_logic_vector ( 1 downto 0 ) |
| RIO refclks, negative. | |
| CLK_TOP | in std_logic |
| 4x Bunch Clock | |
| CLK_BOT | in std_logic |
| 4x Bunch Clock | |
| XTAL_SEL | out std_logic |
| PLL source select. | |
| CLK_DET | in std_logic |
| PLL flag specifying presence of external clock source. | |
| RESET | in std_logic |
| global reset via push button | |
| SOS_LED | out std_logic |
| debug LED | |
| VALID_all | out std_logic |
| RIO status LED. | |
| MASK_IRENA | out std_logic |
| mask data input | |
| MASK_EWA | out std_logic |
| mask data input | |
| MASK_ANDREJ | out std_logic |
| mask data input | |
| MASK_HEINZ | out std_logic |
| mask data input | |
| MASK_MARKO | out std_logic |
| mask data input | |
| MASK_WILLIAM | out std_logic |
| mask data input | |
| MASK_HARRIS | out std_logic |
| mask data input | |
| MASK_HELMUT | out std_logic |
| mask data input | |
| RXN_C_IE | in std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs neg. | |
| RXP_C_IE | in std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs pos. | |
| RXN_C_AH | in std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs neg. | |
| RXP_C_AH | in std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs pos. | |
| RXN_A_WM | in std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs neg. | |
| RXP_A_WM | in std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs pos. | |
| RXN_A_HH | in std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs neg. | |
| RXP_A_HH | in std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs pos. | |
| TXN_C_IE | out std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs neg. | |
| TXP_C_IE | out std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs pos. | |
| TXN_C_AH | out std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs neg. | |
| TXP_C_AH | out std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs pos. | |
| TXN_A_WM | out std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs neg. | |
| TXP_A_WM | out std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs pos. | |
| TXN_A_HH | out std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs neg. | |
| TXP_A_HH | out std_logic_vector ( 1 downto 0 ) |
| RIO 2 CHs pos. | |
| cntrl0_DDR_A | out std_logic_vector ( 12 downto 0 ) |
| DDR address lines. | |
| cntrl0_DDR_BA | out std_logic_vector ( 1 downto 0 ) |
| DDR bank select. | |
| cntrl0_DDR_CKE | out std_logic |
| DDR clock enable. | |
| cntrl0_DDR_CS_N | out std_logic |
| DDR chip select. | |
| cntrl0_DDR_RAS_N | out std_logic |
| DDR row address strobe. | |
| cntrl0_DDR_CAS_N | out std_logic |
| DDR column address strobe. | |
| cntrl0_DDR_WE_N | out std_logic |
| DDR write enable. | |
| cntrl0_DDR_DM | out std_logic_vector ( 3 downto 0 ) |
| DDR data mask. | |
| cntrl0_DDR_CK | out std_logic |
| DDR clock pos. | |
| cntrl0_DDR_CK_N | out std_logic |
| DDR clock neg. | |
| cntrl0_DDR_DQ | inout std_logic_vector ( 31 downto 0 ) |
| DDR data. | |
| cntrl0_DDR_DQS | inout std_logic_vector ( 3 downto 0 ) |
| DDR data strobe. | |
| cntrl0_DDR2_A | out std_logic_vector ( 13 downto 0 ) |
| DDR2 address lines. | |
| cntrl0_DDR2_BA | out std_logic_vector ( 1 downto 0 ) |
| DDR2 bank select. | |
| cntrl0_DDR2_RAS_N | out std_logic |
| DDR2 row address strobe. | |
| cntrl0_DDR2_CAS_N | out std_logic |
| DDR2 column address strobe. | |
| cntrl0_DDR2_WE_N | out std_logic |
| DDR2 write enable. | |
| cntrl0_DDR2_RESET_N | out std_logic |
| DDR2 reset. | |
| cntrl0_DDR2_CS_N | out std_logic |
| DDR2 chip select. | |
| cntrl0_DDR2_ODT | out std_logic |
| DDR2 termination. | |
| cntrl0_DDR2_CKE | out std_logic |
| DDR2 clock enable. | |
| cntrl0_DDR2_DM | out std_logic_vector ( 7 downto 0 ) |
| DDR2 data mask. | |
| cntrl0_DDR2_CK | out std_logic |
| DDR2 clock pos. | |
| cntrl0_DDR2_CK_N | out std_logic |
| DDR2 clock neg. | |
| cntrl0_DDR2_DQ | inout std_logic_vector ( 63 downto 0 ) |
| DDR2 data. | |
| cntrl0_DDR2_DQS | inout std_logic_vector ( 7 downto 0 ) |
| DDR2 data strobe pos. | |
| cntrl0_DDR2_DQS_N | inout std_logic_vector ( 7 downto 0 ) |
| DDR2 data strobe neg. | |
| gmii_rx_clk | in std_logic |
| EMAC PHY RX clk. | |
| gmii_rx_dv | in std_logic |
| EMAC PHY RX valid. | |
| gmii_rx_er | in std_logic |
| EMAC PHY RX error. | |
| gmii_rxd | in std_logic_vector ( 0 to 7 ) |
| EMAC PHY RX data. | |
| mdio | inout std_logic |
| MDIO. | |
| mii_tx_clk | in std_logic |
| EMAC PHY TX clk. | |
| gmii_tx_en | out std_logic |
| EMAC PHY TX enable. | |
| gmii_tx_er | out std_logic |
| EMAC PHY TX error. | |
| gmii_txd | out std_logic_vector ( 0 to 3 ) |
| EMAC PHY TX data. | |
| MDC_0 | out std_logic |
| MDIO. | |
| phy_rst_n | out std_logic |
| EMAC PHY reset. | |
| SL_LFF | in std_logic |
| SLINK, link full flag. | |
| SL_LDOWN | in std_logic |
| SLINK, link down flag. | |
| SL_LRL | in std_logic_vector ( 3 downto 0 ) |
| SLINK, return lines, not used! | |
| SL_UCLK | out std_logic |
| SLINK, clock. | |
| SL_UD | out std_logic_vector ( 31 downto 0 ) |
| SLINK, data. | |
| SL_URESET | out std_logic |
| SLINK, reset. | |
| SL_UTEST | out std_logic |
| SLINK, test line. | |
| SL_UWEN | out std_logic |
| SLINK, write enable. | |
| SL_UCTRL | out std_logic |
| SLINK, control line. | |
| SL_UDW | out std_logic_vector ( 1 downto 0 ) |
| SLINK, data width. | |
| BUSY | out std_logic |
| ROD Busy. | |
| ORBIT | in std_logic |
| ORBIT from LTP. | |
| L1A | in std_logic |
| ATLAS Level-1 Accept. | |
| TRIGGER_TYPE | in std_logic_vector ( 8 downto 1 ) |
| L1A Type identification. | |
| ECR | in std_logic |
| Event Counter Reset. | |
| BCR | in std_logic |
| Bunch Counter Reset. | |
| CTP | out std_logic_vector ( 9 downto 1 ) |
| CTP Inputs we provide. | |
| POST_LOCK | in std_logic |
| Post Lock. | |
| INJECT_PERM_1 | out std_logic |
| Injection Permit 1. | |
| INJECT_PERM_2 | out std_logic |
| Injection Permit 2. | |
| BEAM_PERM_1 | out std_logic |
| Beam Permit 1. | |
| BEAM_PERM_2 | out std_logic |
| Beam Permit 2. | |
| DSS_WARNING_1 | out std_logic |
| DSS Warning 1. | |
| DSS_WARNING_2 | out std_logic |
| DSS Warning 2. | |
| DSS_ABORT_1 | out std_logic |
| DSS Abort 1. | |
| DSS_ABORT_2 | out std_logic |
| DSS Abort 2. | |
| RXP_SATA_IN | in std_logic_vector ( 1 downto 0 ) |
| SATA P inputs. | |
| RXN_SATA_IN | in std_logic_vector ( 1 downto 0 ) |
| SATA N inputs. | |
| TXP_SATA_OUT | out std_logic_vector ( 1 downto 0 ) |
| SATA P outputs. | |
| TXN_SATA_OUT | out std_logic_vector ( 1 downto 0 ) |
| SATA N outputs. | |
| LCD_E | out std_logic |
| LCD, enable. | |
| LCD_RS | out std_logic |
| LCD, status. | |
| LCD_RW | out std_logic |
| LCD, read/write. | |
| LCD_DIRECTION | out std_logic |
| LCD, data direction. | |
| LCD_DB | inout std_logic_vector ( 7 downto 0 ) |
| LCD, data, used for status LEDs if LCD controller is disabled. | |
Detailed Description
top module of BCM AAA designThis entity is the top module of the complete BCM AAA FPGA design. All the ports directly interface to the world outside. All the main control FSMs are in here and the major global components are instantiated here.
- Todo:
- put proper doxy-comments into all files
update documentation for completeness
- Bug:
- post-mortem dump communication with rx program
Definition at line 135 of file bcm_aaa.vhd.
Member Data Documentation
BCR in std_logic [Port] |
BEAM_PERM_1 out std_logic [Port] |
BEAM_PERM_2 out std_logic [Port] |
build_parameters package [Package] |
BUSY out std_logic [Port] |
CLK_BOT in std_logic [Port] |
CLK_DET in std_logic [Port] |
CLK_TOP in std_logic [Port] |
cntrl0_DDR2_A out std_logic_vector ( 13 downto 0 ) [Port] |
cntrl0_DDR2_BA out std_logic_vector ( 1 downto 0 ) [Port] |
cntrl0_DDR2_CAS_N out std_logic [Port] |
cntrl0_DDR2_CK out std_logic [Port] |
cntrl0_DDR2_CK_N out std_logic [Port] |
cntrl0_DDR2_CKE out std_logic [Port] |
cntrl0_DDR2_CS_N out std_logic [Port] |
cntrl0_DDR2_DM out std_logic_vector ( 7 downto 0 ) [Port] |
cntrl0_DDR2_DQ inout std_logic_vector ( 63 downto 0 ) [Port] |
cntrl0_DDR2_DQS inout std_logic_vector ( 7 downto 0 ) [Port] |
cntrl0_DDR2_DQS_N inout std_logic_vector ( 7 downto 0 ) [Port] |
cntrl0_DDR2_ODT out std_logic [Port] |
cntrl0_DDR2_RAS_N out std_logic [Port] |
cntrl0_DDR2_RESET_N out std_logic [Port] |
cntrl0_DDR2_WE_N out std_logic [Port] |
cntrl0_DDR_A out std_logic_vector ( 12 downto 0 ) [Port] |
cntrl0_DDR_BA out std_logic_vector ( 1 downto 0 ) [Port] |
cntrl0_DDR_CAS_N out std_logic [Port] |
cntrl0_DDR_CK out std_logic [Port] |
cntrl0_DDR_CK_N out std_logic [Port] |
cntrl0_DDR_CKE out std_logic [Port] |
cntrl0_DDR_CS_N out std_logic [Port] |
cntrl0_DDR_DM out std_logic_vector ( 3 downto 0 ) [Port] |
cntrl0_DDR_DQ inout std_logic_vector ( 31 downto 0 ) [Port] |
cntrl0_DDR_DQS inout std_logic_vector ( 3 downto 0 ) [Port] |
cntrl0_DDR_RAS_N out std_logic [Port] |
cntrl0_DDR_WE_N out std_logic [Port] |
CTP out std_logic_vector ( 9 downto 1 ) [Port] |
DSS_ABORT_1 out std_logic [Port] |
DSS_ABORT_2 out std_logic [Port] |
DSS_WARNING_1 out std_logic [Port] |
DSS_WARNING_2 out std_logic [Port] |
ECR in std_logic [Port] |
gmii_rx_clk in std_logic [Port] |
gmii_rx_dv in std_logic [Port] |
gmii_rx_er in std_logic [Port] |
gmii_rxd in std_logic_vector ( 0 to 7 ) [Port] |
gmii_tx_en out std_logic [Port] |
gmii_tx_er out std_logic [Port] |
gmii_txd out std_logic_vector ( 0 to 3 ) [Port] |
ieee library [Library] |
INJECT_PERM_1 out std_logic [Port] |
INJECT_PERM_2 out std_logic [Port] |
L1A in std_logic [Port] |
LCD_DB inout std_logic_vector ( 7 downto 0 ) [Port] |
LCD, data, used for status LEDs if LCD controller is disabled.
Definition at line 255 of file bcm_aaa.vhd.
LCD_DIRECTION out std_logic [Port] |
LCD_E out std_logic [Port] |
LCD_RS out std_logic [Port] |
LCD_RW out std_logic [Port] |
main_components package [Package] |
MASK_ANDREJ out std_logic [Port] |
MASK_EWA out std_logic [Port] |
MASK_HARRIS out std_logic [Port] |
MASK_HEINZ out std_logic [Port] |
MASK_HELMUT out std_logic [Port] |
MASK_IRENA out std_logic [Port] |
MASK_MARKO out std_logic [Port] |
MASK_WILLIAM out std_logic [Port] |
MDC_0 out std_logic [Port] |
mdio inout std_logic [Port] |
mii_tx_clk in std_logic [Port] |
numeric_std package [Package] |
arithmetic functions & operators for signed & unsigned datatypes, see file
Definition at line 115 of file bcm_aaa.vhd.
ORBIT in std_logic [Port] |
phy_rst_n out std_logic [Port] |
POST_LOCK in std_logic [Port] |
RESET in std_logic [Port] |
RXN_A_HH in std_logic_vector ( 1 downto 0 ) [Port] |
RXN_A_WM in std_logic_vector ( 1 downto 0 ) [Port] |
RXN_C_AH in std_logic_vector ( 1 downto 0 ) [Port] |
RXN_C_IE in std_logic_vector ( 1 downto 0 ) [Port] |
RXN_SATA_IN in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_A_HH in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_A_WM in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_C_AH in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_C_IE in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_SATA_IN in std_logic_vector ( 1 downto 0 ) [Port] |
SL_LDOWN in std_logic [Port] |
SL_LFF in std_logic [Port] |
SL_LRL in std_logic_vector ( 3 downto 0 ) [Port] |
SL_UCLK out std_logic [Port] |
SL_UCTRL out std_logic [Port] |
SL_UD out std_logic_vector ( 31 downto 0 ) [Port] |
SL_UDW out std_logic_vector ( 1 downto 0 ) [Port] |
SL_URESET out std_logic [Port] |
SL_UTEST out std_logic [Port] |
SL_UWEN out std_logic [Port] |
SOS_LED out std_logic [Port] |
std_logic_1164 package [Package] |
std_logic_arith package [Package] |
std_logic_unsigned package [Package] |
unsigned functions & operators for std_logic_vector type, see file
Definition at line 113 of file bcm_aaa.vhd.
SYSCLK in std_logic [Port] |
TRIGGER_TYPE in std_logic_vector ( 8 downto 1 ) [Port] |
TXN_A_HH out std_logic_vector ( 1 downto 0 ) [Port] |
TXN_A_WM out std_logic_vector ( 1 downto 0 ) [Port] |
TXN_C_AH out std_logic_vector ( 1 downto 0 ) [Port] |
TXN_C_IE out std_logic_vector ( 1 downto 0 ) [Port] |
TXN_SATA_OUT out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_A_HH out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_A_WM out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_C_AH out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_C_IE out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_SATA_OUT out std_logic_vector ( 1 downto 0 ) [Port] |
unisim library [Library] |
UPPER_MGTCLK_PAD_N_IN_EX in std_logic_vector ( 1 downto 0 ) [Port] |
UPPER_MGTCLK_PAD_P_IN_EX in std_logic_vector ( 1 downto 0 ) [Port] |
VALID_all out std_logic [Port] |
vcomponents package [Package] |
work library [Library] |
XTAL_SEL out std_logic [Port] |
The documentation for this class was generated from the following file:
