ADDSUB48 Entity Reference
Virtex-4 DSP48 Core Wrapper. More...
Inheritance diagram for ADDSUB48:
Collaboration diagram for ADDSUB48:
Architectures | |
| ADDSUB48_ARCH | Architecture |
| Virtex-4 DSP48 Core Wrapper. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CLK | in std_logic |
| Clock. | |
| RST | in std_logic |
| Reset. | |
| C_IN | in std_logic_vector ( 6 downto 0 ) |
 | |
| PC_IN | in std_logic_vector ( 6 downto 0 ) |
 | |
| RESULT | out std_logic_vector ( 6 downto 0 ) |
| Result, obviously. | |
Detailed Description
Virtex-4 DSP48 Core Wrapper.
VHDL instantiation template for DSP48 embedded MAC blocks arranged as a single 48 bit Add/Sub unit. The macro uses 1 DSP slice. The output is C - (0 + A&B). A = 0, B = C_IN, C = PC_IN Afterwards the absolute value of the result is formed.
Definition at line 62 of file addsub48.vhd.
Member Data Documentation
C_IN in std_logic_vector ( 6 downto 0 ) [Port] |
CLK in std_logic [Port] |
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 43 of file addsub48.vhd.
PC_IN in std_logic_vector ( 6 downto 0 ) [Port] |
RESULT out std_logic_vector ( 6 downto 0 ) [Port] |
RST in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic_arith package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 47 of file addsub48.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
