ddr2_mem_RAM_D_0 Entity Reference
DistRAM to buffer data. More...
Inheritance diagram for ddr2_mem_RAM_D_0:
Collaboration diagram for ddr2_mem_RAM_D_0:
Architectures | |
| arc_RAM | Architecture |
| DistRAM to buffer data. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| work | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| ddr2_mem_parameters_0 | Package <ddr2_mem_parameters_0> |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| DPO | out std_logic_vector ( memory_width-1 downto 0 ) |
| A0 | in std_logic |
| A1 | in std_logic |
| A2 | in std_logic |
| A3 | in std_logic |
| D | in std_logic_vector ( memory_width-1 downto 0 ) |
| DPRA0 | in std_logic |
| DPRA1 | in std_logic |
| DPRA2 | in std_logic |
| DPRA3 | in std_logic |
| WCLK | in std_logic |
| WE | in std_logic |
Detailed Description
DistRAM to buffer data.Contains the distributed RAM which stores IOB output data that is read from the memory.
Definition at line 61 of file ddr2_mem_RAM_D_0.vhd.
Member Data Documentation
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 48 of file ddr2_mem_RAM_D_0.vhd.
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 46 of file ddr2_mem_RAM_D_0.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
