ddr_chksum_accu Entity Reference

32-bit DSP accumulator More...

Inheritance diagram for ddr_chksum_accu:

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Collaboration diagram for ddr_chksum_accu:

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List of all members.


Architectures

BEHAVIORAL Architecture
 32-bit DSP accumulator More...

Libraries

ieee 
 standard IEEE library
unisim 
 Library with Xilinx primitives.

Packages

std_logic_1164 
 std_logic definitions, see file
numeric_std 
 arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Vcomponents 

Ports

AB_IN  in std_logic_vector ( 31 downto 0 )
CEA_IN  in std_logic
CEB_IN  in std_logic
CECTRL_IN  in std_logic
CEM_IN  in std_logic
CEP_IN  in std_logic
CLK_IN  in std_logic
LOAD_IN  in std_logic
RSTA_IN  in std_logic
RSTB_IN  in std_logic
RSTCTRL_IN  in std_logic
RSTM_IN  in std_logic
RSTP_IN  in std_logic
BCOUT_OUT  out std_logic_vector ( 17 downto 0 )
PCOUT_OUT  out std_logic_vector ( 47 downto 0 )
P_OUT  out std_logic_vector ( 47 downto 0 )


Detailed Description

32-bit DSP accumulator

Definition at line 56 of file ddr_chksum_accu.vhd.


Member Data Documentation

ieee library [Library]

standard IEEE library

Definition at line 46 of file ddr_chksum_accu.vhd.

numeric_std package [Package]

arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file

Definition at line 50 of file ddr_chksum_accu.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Definition at line 48 of file ddr_chksum_accu.vhd.

unisim library [Library]

Library with Xilinx primitives.

Definition at line 52 of file ddr_chksum_accu.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 00:50:59 2008 for BCM-AAA by doxygen 1.5.7.1-20081012