generic_shift_reg Entity Reference
Generic shift register. Width and depth adjustable at compile-time. More...
Inheritance diagram for generic_shift_reg:
Collaboration diagram for generic_shift_reg:
Architectures | |
| generic_shift_reg_arc | Architecture |
| Generic shift register. Width and depth adjustable at compile-time. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
Generics | |
| WIDTH | positive range 1 to 255 := 1 |
| shift register width | |
| DEPTH | positive range 1 to 255 := 1 |
| shift register depth | |
Ports | |
| CLK | in std_logic |
| clock | |
| RES | in std_logic |
| reset | |
| DIN | in std_logic_vector ( width-1 downto 0 ) |
| data in | |
| DOUT | out std_logic_vector ( width-1 downto 0 ) |
| shifted data out | |
Detailed Description
Generic shift register. Width and depth adjustable at compile-time.Definition at line 31 of file generic_shift_reg.vhd.
Member Data Documentation
CLK in std_logic [Port] |
DEPTH positive range 1 to 255 := 1 [Generic] |
DIN in std_logic_vector ( width-1 downto 0 ) [Port] |
DOUT out std_logic_vector ( width-1 downto 0 ) [Port] |
ieee library [Library] |
standard IEEE library
Reimplemented in main_components.
Definition at line 25 of file generic_shift_reg.vhd.
RES in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 27 of file generic_shift_reg.vhd.
WIDTH positive range 1 to 255 := 1 [Generic] |
The documentation for this class was generated from the following file:
