clocks Entity Reference

central clock module More...

Inheritance diagram for clocks:

Collaboration diagram for clocks:

List of all members.

Architectures

coldplay Architecture

central clock module More...

Libraries

ieee

standard IEEE library

unisim

Library with Xilinx primitives.

Packages

std_logic_1164

std_logic definitions, see file

std_logic_arith

arithmetic operations on std_logic datatypes, see file

std_logic_unsigned

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

vcomponents

Header with Xilinx primitives.

Ports

RESET in std_logic

global reset

SYSCLK in std_logic

100 MHz from ML410

REFCLK in std_logic

200 MHz in, deprecated

BCLK4X in std_logic

160 MHz from ext. PLL

UPPER_MGTCLK_PAD_P_IN_EX in std_logic_vector ( 1 downto 0 )

RIO refclks, positive.

UPPER_MGTCLK_PAD_N_IN_EX in std_logic_vector ( 1 downto 0 )

RIO refclks, negative.

SYSCLK_INT out std_logic

100 MHz out

DDRCLK out std_logic

160 MHz out

REFCLK_P out std_logic

200 MHz out

REFCLK_N out std_logic

200 MHz out shifted by $180^{\circ}$

BCLK out std_logic

40 MHz out

BCLK2X_P out std_logic

80 MHz out

BCLK2X_N out std_logic

80 MHz out shifted by $180^{\circ}$ , deprecated

BCLK4X_P out std_logic

160 MHz out

BCLK4X_N out std_logic

160 MHz out shifted by $180^{\circ}$ , deprecated

RIOCLK_1 out std_logic

160 MHz for RIOs

RIOCLK_2 out std_logic

160 MHz for RIOs

SATA_CLK out std_logic

160 MHz for SATA

SATA_LOGIC_CLK out std_logic

80 MHz for SATA logic

CLK_50MHz_OUT out std_logic

50 MHz for SATA

EMAC_CLK out std_logic

100 MHz for EMAC

INTTRIG_CLK out std_logic

slow clock for internal trigger generation

CLK_HZ out std_logic

1 Hz Clock

XTAL_SEL out std_logic

Select source for external PLL, 0 = BC, 1 = int. Oscillator.

CLK_DET in std_logic

Flag from ext. PLL, 0 = BC not available, 1 = BC present.

LOCK out std_logic

lock flag of all DCMs

Detailed Description

central clock module

In this module all input clocks are buffered and put on global clock nets. All the various clocks that are needed for the main modules in the design are derived from the external input clocks

Definition at line 41 of file clocks.vhd.

Member Data Documentation

BCLK out std_logic [Port]

40 MHz out

Definition at line 52 of file clocks.vhd.

BCLK2X_N out std_logic [Port]

80 MHz out shifted by $180^{\circ}$ , deprecated

Definition at line 54 of file clocks.vhd.

BCLK2X_P out std_logic [Port]

80 MHz out

Definition at line 53 of file clocks.vhd.

BCLK4X in std_logic [Port]

160 MHz from ext. PLL

Definition at line 45 of file clocks.vhd.

BCLK4X_N out std_logic [Port]

160 MHz out shifted by $180^{\circ}$ , deprecated

Definition at line 56 of file clocks.vhd.

BCLK4X_P out std_logic [Port]

160 MHz out

Definition at line 55 of file clocks.vhd.

CLK_50MHz_OUT out std_logic [Port]

50 MHz for SATA

Definition at line 61 of file clocks.vhd.

CLK_DET in std_logic [Port]

Flag from ext. PLL, 0 = BC not available, 1 = BC present.

Definition at line 66 of file clocks.vhd.

CLK_HZ out std_logic [Port]

1 Hz Clock

Definition at line 64 of file clocks.vhd.

DDRCLK out std_logic [Port]

160 MHz out

Definition at line 49 of file clocks.vhd.

EMAC_CLK out std_logic [Port]

100 MHz for EMAC

Definition at line 62 of file clocks.vhd.

ieee library [Library]

standard IEEE library

Reimplemented in main_components.

Definition at line 24 of file clocks.vhd.

INTTRIG_CLK out std_logic [Port]

slow clock for internal trigger generation

Definition at line 63 of file clocks.vhd.

LOCK out std_logic [Port]

lock flag of all DCMs

Definition at line 67 of file clocks.vhd.

REFCLK in std_logic [Port]

200 MHz in, deprecated

Definition at line 44 of file clocks.vhd.

REFCLK_N out std_logic [Port]

200 MHz out shifted by $180^{\circ}$

Definition at line 51 of file clocks.vhd.

REFCLK_P out std_logic [Port]

200 MHz out

Definition at line 50 of file clocks.vhd.

RESET in std_logic [Port]

global reset

Definition at line 42 of file clocks.vhd.

RIOCLK_1 out std_logic [Port]

160 MHz for RIOs

Definition at line 57 of file clocks.vhd.

RIOCLK_2 out std_logic [Port]

160 MHz for RIOs

Definition at line 58 of file clocks.vhd.

SATA_CLK out std_logic [Port]

160 MHz for SATA

Definition at line 59 of file clocks.vhd.

SATA_LOGIC_CLK out std_logic [Port]

80 MHz for SATA logic

Definition at line 60 of file clocks.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Reimplemented in main_components.

Definition at line 26 of file clocks.vhd.

std_logic_arith package [Package]

arithmetic operations on std_logic datatypes, see file

Definition at line 28 of file clocks.vhd.

std_logic_unsigned package [Package]

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

Definition at line 30 of file clocks.vhd.

SYSCLK in std_logic [Port]

100 MHz from ML410

Definition at line 43 of file clocks.vhd.

SYSCLK_INT out std_logic [Port]

100 MHz out

Definition at line 48 of file clocks.vhd.

unisim library [Library]

Library with Xilinx primitives.

Definition at line 32 of file clocks.vhd.

UPPER_MGTCLK_PAD_N_IN_EX in std_logic_vector ( 1 downto 0 ) [Port]

RIO refclks, negative.

Definition at line 47 of file clocks.vhd.

UPPER_MGTCLK_PAD_P_IN_EX in std_logic_vector ( 1 downto 0 ) [Port]

RIO refclks, positive.

Definition at line 46 of file clocks.vhd.

vcomponents package [Package]

Header with Xilinx primitives.

Definition at line 34 of file clocks.vhd.

XTAL_SEL out std_logic [Port]

Select source for external PLL, 0 = BC, 1 = int. Oscillator.

Definition at line 65 of file clocks.vhd.

The documentation for this class was generated from the following file:

clocks.vhd


Architectures
coldplay	Architecture
	central clock module More...
Libraries
ieee
	standard IEEE library
unisim
	Library with Xilinx primitives.
Packages
std_logic_1164
	std_logic definitions, see file
std_logic_arith
	arithmetic operations on std_logic datatypes, see file
std_logic_unsigned
	unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
vcomponents
	Header with Xilinx primitives.
Ports
RESET	in std_logic
	global reset
SYSCLK	in std_logic
	100 MHz from ML410
REFCLK	in std_logic
	200 MHz in, deprecated
BCLK4X	in std_logic
	160 MHz from ext. PLL
UPPER_MGTCLK_PAD_P_IN_EX	in std_logic_vector ( 1 downto 0 )
	RIO refclks, positive.
UPPER_MGTCLK_PAD_N_IN_EX	in std_logic_vector ( 1 downto 0 )
	RIO refclks, negative.
SYSCLK_INT	out std_logic
	100 MHz out
DDRCLK	out std_logic
	160 MHz out
REFCLK_P	out std_logic
	200 MHz out
REFCLK_N	out std_logic
	200 MHz out shifted by $180^{\circ}$
BCLK	out std_logic
	40 MHz out
BCLK2X_P	out std_logic
	80 MHz out
BCLK2X_N	out std_logic
	80 MHz out shifted by $180^{\circ}$ , deprecated
BCLK4X_P	out std_logic
	160 MHz out
BCLK4X_N	out std_logic
	160 MHz out shifted by $180^{\circ}$ , deprecated
RIOCLK_1	out std_logic
	160 MHz for RIOs
RIOCLK_2	out std_logic
	160 MHz for RIOs
SATA_CLK	out std_logic
	160 MHz for SATA
SATA_LOGIC_CLK	out std_logic
	80 MHz for SATA logic
CLK_50MHz_OUT	out std_logic
	50 MHz for SATA
EMAC_CLK	out std_logic
	100 MHz for EMAC
INTTRIG_CLK	out std_logic
	slow clock for internal trigger generation
CLK_HZ	out std_logic
	1 Hz Clock
XTAL_SEL	out std_logic
	Select source for external PLL, 0 = BC, 1 = int. Oscillator.
CLK_DET	in std_logic
	Flag from ext. PLL, 0 = BC not available, 1 = BC present.
LOCK	out std_logic
	lock flag of all DCMs