delay_adj.delay_adj_arc Architecture Reference

Fine delay for 2 RocketIO channels. More...

Inheritance diagram for delay_adj.delay_adj_arc:

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Collaboration diagram for delay_adj.delay_adj_arc:

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List of all members.

Processes
PROCESS_167	( CLK )
	64-bit wide shift register with parallel read/write
Signals
a_i	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
b_i	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )

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Detailed Description

Fine delay for 2 RocketIO channels.

Data can be shifted by taps, latency is 1 clock cycle. Delay value can be set at runtime.

Definition at line 50 of file delay_adj.vhd.

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Member Function Documentation

[Process]

PROCESS_167

( CLK )

64-bit wide shift register with parallel read/write

Definition at line 58 of file delay_adj.vhd.

  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      a_i <= A & a_i(63 downto 32);
      b_i <= B & b_i(63 downto 32);
      X   <= a_i(63-ADJ_TIME_1 downto 32-ADJ_TIME_1);
      Y   <= b_i(63-ADJ_TIME_2 downto 32-ADJ_TIME_2);
    end if;
  end process;

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The documentation for this class was generated from the following file:

• delay_adj.vhd