ddr2_mem_rd_data_0.arc_rd_data Architecture Reference

Read datapath. More...

Inheritance diagram for ddr2_mem_rd_data_0.arc_rd_data:

Collaboration diagram for ddr2_mem_rd_data_0.arc_rd_data:

List of all members.

Processes

PROCESS_138 ( CLK )

enable shift

Components

ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>

FIFO.

ddr2_mem_pattern_compare4

Pattern comparator.

ddr2_mem_pattern_compare8 <Entity ddr2_mem_pattern_compare8>

Pattern comparator.

Signals

read_data_valid0 std_logic

read_data_valid1 std_logic

read_data_valid2 std_logic

read_data_valid3 std_logic

read_data_valid4 std_logic

read_data_valid5 std_logic

read_data_valid6 std_logic

read_data_valid7 std_logic

read_data_valid8 std_logic

COMP_DONE_int std_logic_vector ( ReadEnable-1 downto 0 )

FIRST_RISING_int std_logic_vector ( ReadEnable-1 downto 0 )

READ_EN_DELAYED_RISE std_logic_vector ( ReadEnable-1 downto 0 )

READ_EN_DELAYED_FALL std_logic_vector ( ReadEnable-1 downto 0 )

fifo_read_enable_r std_logic

fifo_read_enable_2r std_logic

Component Instantiations

pattern_0 ddr2_mem_pattern_compare8 <Entity ddr2_mem_pattern_compare8>

Pattern comparator.

pattern_1 ddr2_mem_pattern_compare8 <Entity ddr2_mem_pattern_compare8>

Pattern comparator.

rd_data_fifo0 ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>

FIFO.

rd_data_fifo1 ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>

FIFO.

rd_data_fifo2 ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>

FIFO.

rd_data_fifo3 ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>

FIFO.

rd_data_fifo4 ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>

FIFO.

rd_data_fifo5 ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>

FIFO.

rd_data_fifo6 ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>

FIFO.

rd_data_fifo7 ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>

FIFO.

Detailed Description

Read datapath.

The delay between the read data with respect to the command issued is calculted in terms of no. of clocks. This data is then stored into the FIFOs and then read back and given as the ouput for comparison.

Definition at line 82 of file ddr2_mem_rd_data_0.vhd.

Member Function Documentation

[Process]

PROCESS_138 ( CLK )

enable shift

Definition at line 151 of file ddr2_mem_rd_data_0.vhd.

00151   process(CLK)
00152   begin
00153     if (CLK'event and CLK = '1') then
00154       if (RESET = '1') then
00155         fifo_read_enable_r  <= '0';
00156         fifo_read_enable_2r <= '0';
00157       else
00158         fifo_read_enable_r  <= READ_EN_DELAYED_RISE(0);
00159         fifo_read_enable_2r <= fifo_read_enable_r;
00160       end if;
00161     end if;
00162   end process;

Member Data Documentation

ddr2_mem_pattern_compare4 [Component]

Pattern comparator.

Definition at line 102 of file ddr2_mem_rd_data_0.vhd.

ddr2_mem_pattern_compare8 [Component]

Pattern comparator.

Definition at line 116 of file ddr2_mem_rd_data_0.vhd.

ddr2_mem_rd_data_fifo_0 [Component]

FIFO.

Definition at line 85 of file ddr2_mem_rd_data_0.vhd.

pattern_0 ddr2_mem_pattern_compare8 [Component Instantiation]

Pattern comparator.

Definition at line 165 of file ddr2_mem_rd_data_0.vhd.

pattern_1 ddr2_mem_pattern_compare8 [Component Instantiation]

Pattern comparator.

Definition at line 178 of file ddr2_mem_rd_data_0.vhd.

rd_data_fifo0 ddr2_mem_rd_data_fifo_0 [Component Instantiation]

FIFO.

Definition at line 191 of file ddr2_mem_rd_data_0.vhd.

rd_data_fifo1 ddr2_mem_rd_data_fifo_0 [Component Instantiation]

FIFO.

Definition at line 207 of file ddr2_mem_rd_data_0.vhd.

rd_data_fifo2 ddr2_mem_rd_data_fifo_0 [Component Instantiation]

FIFO.

Definition at line 223 of file ddr2_mem_rd_data_0.vhd.

rd_data_fifo3 ddr2_mem_rd_data_fifo_0 [Component Instantiation]

FIFO.

Definition at line 239 of file ddr2_mem_rd_data_0.vhd.

rd_data_fifo4 ddr2_mem_rd_data_fifo_0 [Component Instantiation]

FIFO.

Definition at line 255 of file ddr2_mem_rd_data_0.vhd.

rd_data_fifo5 ddr2_mem_rd_data_fifo_0 [Component Instantiation]

FIFO.

Definition at line 271 of file ddr2_mem_rd_data_0.vhd.

rd_data_fifo6 ddr2_mem_rd_data_fifo_0 [Component Instantiation]

FIFO.

Definition at line 287 of file ddr2_mem_rd_data_0.vhd.

rd_data_fifo7 ddr2_mem_rd_data_fifo_0 [Component Instantiation]

FIFO.

Definition at line 303 of file ddr2_mem_rd_data_0.vhd.

The documentation for this class was generated from the following file:

ddr2_mem_rd_data_0.vhd


Processes
PROCESS_138	( CLK )
	enable shift
Components
ddr2_mem_rd_data_fifo_0	<Entity ddr2_mem_rd_data_fifo_0>
	FIFO.
ddr2_mem_pattern_compare4
	Pattern comparator.
ddr2_mem_pattern_compare8	<Entity ddr2_mem_pattern_compare8>
	Pattern comparator.
Signals
read_data_valid0	std_logic
read_data_valid1	std_logic
read_data_valid2	std_logic
read_data_valid3	std_logic
read_data_valid4	std_logic
read_data_valid5	std_logic
read_data_valid6	std_logic
read_data_valid7	std_logic
read_data_valid8	std_logic
COMP_DONE_int	std_logic_vector ( ReadEnable-1 downto 0 )
FIRST_RISING_int	std_logic_vector ( ReadEnable-1 downto 0 )
READ_EN_DELAYED_RISE	std_logic_vector ( ReadEnable-1 downto 0 )
READ_EN_DELAYED_FALL	std_logic_vector ( ReadEnable-1 downto 0 )
fifo_read_enable_r	std_logic
fifo_read_enable_2r	std_logic
Component Instantiations
pattern_0	ddr2_mem_pattern_compare8 <Entity ddr2_mem_pattern_compare8>
	Pattern comparator.
pattern_1	ddr2_mem_pattern_compare8 <Entity ddr2_mem_pattern_compare8>
	Pattern comparator.
rd_data_fifo0	ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>
	FIFO.
rd_data_fifo1	ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>
	FIFO.
rd_data_fifo2	ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>
	FIFO.
rd_data_fifo3	ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>
	FIFO.
rd_data_fifo4	ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>
	FIFO.
rd_data_fifo5	ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>
	FIFO.
rd_data_fifo6	ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>
	FIFO.
rd_data_fifo7	ddr2_mem_rd_data_fifo_0 <Entity ddr2_mem_rd_data_fifo_0>
	FIFO.