ddr2_mem_infrastructure Entity Reference
Services for DDR2 memory controller. More...
Inheritance diagram for ddr2_mem_infrastructure:
Collaboration diagram for ddr2_mem_infrastructure:
Architectures | |
| arc_infrastructure | Architecture |
| Services for DDR2 memory controller. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| SYS_RESET_IN | in std_logic |
| SYS_CLK_P | in std_logic |
| SYS_CLK_N | in std_logic |
| CLK200_P | in std_logic |
| CLK200_N | in std_logic |
| LOCK | in std_logic |
| CLK | out std_logic |
| CLK90 | out std_logic |
| CLK50 | out std_logic |
| CLK200 | out std_logic |
| REFRESH_CLK | out std_logic |
| sys_rst | out std_logic |
| sys_rst90 | out std_logic |
| sys_rst_ref_clk_1 | out std_logic |
Detailed Description
Services for DDR2 memory controller.This module instantiates the DCM of the FPGA device. The system clock is given as the input and two clocks that are phase shifted by 90 degrees are taken out. It also give the reset signals in phase with the clocks.
Definition at line 59 of file ddr2_mem_infrastructure.vhd.
Member Data Documentation
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 48 of file ddr2_mem_infrastructure.vhd.
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 46 of file ddr2_mem_infrastructure.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
