edge_det.new2 Architecture Reference
Data edge detection. More...
Inheritance diagram for edge_det.new2:
Collaboration diagram for edge_det.new2:
Processes | |
| PROCESS_168 | ( CLK ) |
| pipelined search algo | |
Signals | |
| index_p1_latch | sixteen |
| index_n1_latch | sixteen |
| index_p_low | eight |
| index_n_low | eight |
| index_p1_latch2 | four |
| index_n1_latch2 | four |
| index_p1_latch3 | four |
| index_n1_latch3 | four |
| sum1_n | twofour |
| sum2_n | fivetwo |
| sum1_p | twofour |
| sum2_p | fivetwo |
| data_old | std_logic_vector ( 2 downto 0 ) := " 000 " |
| data_i | std_logic_vector ( 34 downto 0 ) := ( others = > ' 0 ' ) |
| data_ii | std_logic_vector ( 34 downto 0 ) := ( others = > ' 0 ' ) |
| data_i_filt | std_logic_vector ( 34 downto 0 ) := ( others = > ' 0 ' ) |
| data_ii_filt | std_logic_vector ( 34 downto 0 ) := ( others = > ' 0 ' ) |
| fdata_i | std_logic_vector ( 34 downto 0 ) := ( others = > ' 0 ' ) |
| fdata_ii | std_logic_vector ( 34 downto 0 ) := ( others = > ' 0 ' ) |
| edge_det_p | std_logic_vector ( 32 downto 1 ) := ( others = > ' 0 ' ) |
| edge_det_p2 | std_logic_vector ( 32 downto 1 ) := ( others = > ' 0 ' ) |
| edge_det_n | std_logic_vector ( 32 downto 1 ) := ( others = > ' 0 ' ) |
| status1_p1 | std_logic_vector ( 8 downto 1 ) := " 00000000 " |
| status11_p1 | std_logic_vector ( 4 downto 1 ) := " 0000 " |
| status2_p1 | std_logic_vector ( 2 downto 1 ) := " 00 " |
| status1_p2 | std_logic_vector ( 2 downto 1 ) := " 00 " |
| status12_p2 | std_logic := ' 0 ' |
| status1_p3 | std_logic_vector ( 2 downto 1 ) := " 00 " |
| status12_p3 | std_logic := ' 0 ' |
| status1_n1 | std_logic_vector ( 8 downto 1 ) := " 00000000 " |
| status11_n1 | std_logic_vector ( 4 downto 1 ) := " 0000 " |
| status2_n1 | std_logic_vector ( 2 downto 1 ) := " 00 " |
| status_i_p1 | std_logic := ' 0 ' |
| status_i_n1 | std_logic := ' 0 ' |
| status1_n2 | std_logic_vector ( 2 downto 1 ) := " 00 " |
| status12_n2 | std_logic := ' 0 ' |
| status1_n3 | std_logic_vector ( 2 downto 1 ) := " 00 " |
| status12_n3 | std_logic := ' 0 ' |
| index_p1_latch22 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_n1_latch22 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_p1_latch33 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_n1_latch33 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_p1_latch4 | std_logic := ' 0 ' |
| index_n1_latch4 | std_logic := ' 0 ' |
| index_p2_latch | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_p2_latch3 | std_logic_vector ( 2 downto 0 ) := " 000 " |
| index_p2_latch33 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_p2_latch33_1 | std_logic_vector ( 2 downto 0 ) := " 000 " |
| index_p2_out_1 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_p2_out | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_n2_latch | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_n2_latch3 | std_logic_vector ( 2 downto 0 ) := " 000 " |
| index_n2_latch33 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_n2_latch33_1 | std_logic_vector ( 2 downto 0 ) := " 000 " |
| index_n2_out_1 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_n2_out | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_p3_latch | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_p3_latch3 | std_logic_vector ( 2 downto 0 ) := " 000 " |
| index_p3_latch33 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_p3_latch33_1 | std_logic_vector ( 2 downto 0 ) := " 000 " |
| index_p3_out | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_p3_out_1 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_n3_latch | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_n3_latch3 | std_logic_vector ( 2 downto 0 ) := " 000 " |
| index_n3_latch33 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_n3_latch33_1 | std_logic_vector ( 2 downto 0 ) := " 000 " |
| index_n3_out | std_logic_vector ( 1 downto 0 ) := " 00 " |
| index_n3_out_1 | std_logic_vector ( 1 downto 0 ) := " 00 " |
| sum_p | std_logic_vector ( 5 downto 0 ) := " 000000 " |
| sum_n | std_logic_vector ( 5 downto 0 ) := " 000000 " |
| SUM_RIS_i | std_logic_vector ( 5 downto 0 ) := " 000000 " |
| SUM_FAL_i | std_logic_vector ( 5 downto 0 ) := " 000000 " |
| STATUS_P1_i | std_logic := ' 0 ' |
| STATUS_P2_i | std_logic := ' 0 ' |
| STATUS_P3_i | std_logic := ' 0 ' |
| STATUS_N1_i | std_logic := ' 0 ' |
| STATUS_N2_i | std_logic := ' 0 ' |
| STATUS_N3_i | std_logic := ' 0 ' |
| EDGE_RIS1_i | std_logic_vector ( 4 downto 0 ) := " 00000 " |
| EDGE_RIS2_i | std_logic_vector ( 4 downto 0 ) := " 00000 " |
| EDGE_RIS3_i | std_logic_vector ( 4 downto 0 ) := " 00000 " |
| EDGE_FAL1_i | std_logic_vector ( 4 downto 0 ) := " 00000 " |
| EDGE_FAL2_i | std_logic_vector ( 4 downto 0 ) := " 00000 " |
| EDGE_FAL3_i | std_logic_vector ( 4 downto 0 ) := " 00000 " |
Detailed Description
Data edge detection.
This architecture performs the search for both rising and falling edges in the incoming data via pattern matching and then a pipelined binary search tree. The algorithm for the first edge is shown below:
The algorithm for the second and third edge is similar:
Definition at line 76 of file edge_det.vhd.
Member Function Documentation
| PROCESS_168 | ( CLK ) |
pipelined search algo
default to 1!!! default to 1!!!
Definition at line 177 of file edge_det.vhd.
00177 process(CLK) 00178 ------------------------------- variables ------------------------------------- 00179 variable index_p2_latch333 : std_logic_vector (1 downto 0) := "00"; 00180 variable index_n2_latch333 : std_logic_vector (1 downto 0) := "00"; 00181 variable index_p3_latch333 : std_logic_vector (1 downto 0) := "00"; 00182 variable index_n3_latch333 : std_logic_vector (1 downto 0) := "00"; 00183 variable fill1, fill2 : std_logic_vector (34 downto 0) := (others => '0'); 00184 variable edge_det_nh : std_logic_vector (32 downto 1) := (others => '0'); 00185 variable edge_det_ph : std_logic_vector (32 downto 1) := (others => '0'); 00186 variable edge_det_nhh : std_logic_vector (32 downto 1) := (others => '0'); 00187 variable edge_det_phh : std_logic_vector (32 downto 1) := (others => '0'); 00188 variable spike_p : std_logic_vector (32 downto 1) := (others => '1'); 00189 variable spike_n : std_logic_vector (32 downto 1) := (others => '1'); 00190 variable a, b, c, e, f, x, k, l, m, n : std_logic := '0'; 00191 00192 begin 00193 00194 if CLK'event and CLK = '1' then 00195 00196 ------------------------------- default values ------------------------------------- 00197 status1_p1 <= (others => '1'); 00198 status1_n1 <= (others => '1'); 00199 status2_p1 <= (others => '1'); 00200 status2_n1 <= (others => '1'); 00201 spike_n := (others => '1'); 00202 spike_p := (others => '1'); 00203 status_i_p1 <= '1'; 00204 status_i_n1 <= '1'; 00205 status1_p2 <= "11"; 00206 status12_p2 <= '1'; 00207 index_p2_latch3(2 downto 0) <= "111"; 00208 status1_n2 <= "11"; 00209 status12_n2 <= '1'; 00210 index_n2_latch3(2 downto 0) <= "111"; 00211 index_n2_latch33 <= "11"; 00212 index_n2_latch333 := "11"; 00213 status1_p3 <= "11"; 00214 status12_p3 <= '1'; 00215 index_p3_latch3(2 downto 0) <= "111"; 00216 status1_n3 <= "11"; 00217 status12_n3 <= '1'; 00218 index_n3_latch3(2 downto 0) <= "111"; 00219 index_n3_latch33 <= "11"; 00220 index_n3_latch333 := "11"; 00221 00222 data_old <= DATA_IN(2 downto 0); 00223 data_i <= data_old & DATA_IN; 00224 data_ii <= data_i(31 downto 0) & DATA_IN(31 downto 29); 00225 00226 ------------------------------ filtering -------------------------------------- 00227 for i in (DATA_IN'length+2) downto 3 loop --edge det via pattern matching, ris and fal 00228 edge_det_ph(i-2) := ris_hole_pattern(data_i(i downto i-3)); 00229 edge_det_nh(i-2) := fal_hole_pattern(data_i(i downto i-3)); 00230 edge_det_phh(i-2) := ris_hole_pattern(data_ii(i downto i-3)); 00231 edge_det_nhh(i-2) := fal_hole_pattern(data_ii(i downto i-3)); 00232 end loop; 00233 00234 fill1 := ("00" & edge_det_ph & '0') or ('0' & edge_det_nh & "00"); 00235 fill2 := ("00" & edge_det_phh & '0') or ('0' & edge_det_nhh & "00"); 00236 00237 -- data_i2 <= data_i; 00238 -- data_ii2 <= data_ii; 00239 00240 fdata_i <= data_i or fill1; 00241 fdata_ii <= data_ii or fill2; 00242 00243 ----------------------------- spike suppression ----------------------------------- 00244 for i in (DATA_IN'length+2) downto 3 loop 00245 spike_p(i-2) := spike_suppress(fdata_i(i downto i-2)); 00246 spike_n(i-2) := spike_suppress(fdata_ii(i downto i-2)); 00247 end loop; 00248 00249 -- fdata_i2 <= fdata_i; 00250 -- fdata_ii2 <= fdata_ii; 00251 00252 data_i_filt <= fdata_i and ('1' & spike_p & "11"); 00253 data_ii_filt <= fdata_ii and ('1' & spike_n & "11"); 00254 00255 ------------------------------- edge det ------------------------------------- 00256 for i in (DATA_IN'length+2) downto 3 loop --edge det via pattern matching, ris and fal 00257 edge_det_p2(i-2) <= ris_pattern(data_i_filt(i downto i-3)); 00258 edge_det_n(i-2) <= fal_pattern(data_ii_filt(i downto i-3)); 00259 end loop; 00260 00261 edge_det_p <= edge_det_p2; 00262 00263 ------------------------------- pos 1 r & f ------------------------------------- 00264 for m in 1 to 8 loop -- 8 status bits, LSBs of pos1 00265 if edge_det_p((m*4)) = '1' then 00266 index_p1_latch(m) <= "11"; 00267 elsif edge_det_p((m*4)-1) = '1' then 00268 index_p1_latch(m) <= "10"; 00269 elsif edge_det_p((m*4)-2) = '1' then 00270 index_p1_latch(m) <= "01"; 00271 elsif edge_det_p((m*4)-3) = '1' then 00272 index_p1_latch(m) <= "00"; 00273 else 00274 status1_p1(m) <= '0'; 00275 end if; 00276 00277 sum1_p(m) <= conv_std_logic_vector((conv_integer(edge_det_p(m*4)) + 00278 conv_integer(edge_det_p((m*4)-1)) + 00279 conv_integer(edge_det_p((m*4)-2)) + 00280 conv_integer(edge_det_p((m*4)-3))),3); 00281 00282 if edge_det_n((m*4)) = '1' then 00283 index_n1_latch(m) <= "11"; 00284 elsif edge_det_n((m*4)-1) = '1' then 00285 index_n1_latch(m) <= "10"; 00286 elsif edge_det_n((m*4)-2) = '1' then 00287 index_n1_latch(m) <= "01"; 00288 elsif edge_det_n((m*4)-3) = '1' then 00289 index_n1_latch(m) <= "00"; 00290 else 00291 status1_n1(m) <= '0'; 00292 end if; 00293 00294 sum1_n(m) <= conv_std_logic_vector((conv_integer(edge_det_n(m*4)) + 00295 conv_integer(edge_det_n((m*4)-1)) + 00296 conv_integer(edge_det_n((m*4)-2)) + 00297 conv_integer(edge_det_n((m*4)-3))),3); 00298 00299 end loop; 00300 00301 ------------------------------- search top 4 bits for 2nd edge ------------------------------------- 00302 a := dec13 (status1_p1(8 downto 6)); 00303 c := dec13 (status1_n1(8 downto 6)); 00304 00305 if (status1_p1(7) and status1_p1(8)) = '1' then --search top 4 bit for 2nd edge 00306 index_p2_latch3(1 downto 0) <= "10"; 00307 index_p2_latch <= index_p1_latch(7); 00308 elsif (status1_p1(6) and 00309 (status1_p1(7) xor status1_p1(8))) = '1' then 00310 index_p2_latch3(1 downto 0) <= "01"; 00311 index_p2_latch <= index_p1_latch(6); 00312 elsif (status1_p1(5) and a) = '1' then 00313 index_p2_latch3(1 downto 0) <= "00"; 00314 index_p2_latch <= index_p1_latch(5); 00315 else 00316 status12_p2 <= '0'; 00317 index_p2_latch3(2 downto 0) <= "000"; 00318 index_p2_latch <= "00"; 00319 end if; 00320 00321 if (status1_n1(7) and status1_n1(8)) = '1' then 00322 index_n2_latch3(1 downto 0) <= "10"; 00323 index_n2_latch <= index_n1_latch(7); 00324 elsif (status1_n1(6) and (status1_n1(7) xor status1_n1(8))) = '1' then 00325 index_n2_latch3(1 downto 0) <= "01"; 00326 index_n2_latch <= index_n1_latch(6); 00327 elsif (status1_n1(5) and c) = '1' then 00328 index_n2_latch3(1 downto 0) <= "00"; 00329 index_n2_latch <= index_n1_latch(5); 00330 else 00331 status12_n2 <= '0'; 00332 index_n2_latch3(2 downto 0) <= "000"; 00333 index_n2_latch <= "00"; 00334 end if; 00335 00336 --------------------------------- search top 4 bits for 3rd edge ------------------------------------- 00337 k := dec23 (status1_p1(8 downto 6)); 00338 l := dec23 (status1_n1(8 downto 6)); 00339 00340 if (status1_p1(8) and status1_p1(7) and status1_p1(6)) = '1' then --check top 4 bits for 3rd edge 00341 index_p3_latch3(1 downto 0) <= "01"; 00342 index_p3_latch <= index_p1_latch(6); 00343 elsif (k and status1_p1(5)) = '1' then 00344 index_p3_latch3(1 downto 0) <= "00"; 00345 index_p3_latch <= index_p1_latch(5); 00346 else 00347 status12_p3 <= '0'; 00348 index_p3_latch3(2 downto 0) <= "000"; 00349 index_p3_latch <= "00"; 00350 end if; 00351 00352 if (status1_n1(8) and status1_n1(7) and status1_n1(6)) = '1' then 00353 index_n3_latch3(1 downto 0) <= "01"; 00354 index_n3_latch <= index_n1_latch(6); 00355 elsif (l and status1_n1(5)) = '1' then 00356 index_n3_latch3(1 downto 0) <= "00"; 00357 index_n3_latch <= index_n1_latch(5); 00358 else 00359 status12_n3 <= '0'; 00360 index_n3_latch3(2 downto 0) <= "000"; 00361 index_n3_latch <= "00"; 00362 end if; 00363 00364 status11_p1 <= status1_p1(4 downto 1); 00365 status11_n1 <= status1_n1(4 downto 1); 00366 for z in 4 downto 1 loop 00367 index_p_low(z) <= index_p1_latch(z); 00368 index_n_low(z) <= index_n1_latch(z); 00369 end loop; 00370 00371 ------------------------------- next bits pos 1 r & f ------------------------------------- 00372 for j in 1 to 2 loop -- 2 bit status, middle bits of pos1 00373 if status1_p1((j*4)) = '1' then 00374 index_p1_latch3(j) <= "11"; 00375 index_p1_latch2(j) <= index_p1_latch(j*4); 00376 elsif status1_p1((j*4)-1) = '1' then 00377 index_p1_latch3(j) <= "10"; 00378 index_p1_latch2(j) <= index_p1_latch((j*4)-1); 00379 elsif status1_p1((j*4)-2) = '1' then 00380 index_p1_latch3(j) <= "01"; 00381 index_p1_latch2(j) <= index_p1_latch((j*4)-2); 00382 elsif status1_p1((j*4)-3) = '1' then 00383 index_p1_latch3(j) <= "00"; 00384 index_p1_latch2(j) <= index_p1_latch((j*4)-3); 00385 else 00386 status2_p1(j) <= '0'; 00387 index_p1_latch2(j) <= "00"; 00388 end if; 00389 00390 sum2_p(j) <= conv_std_logic_vector((conv_integer(sum1_p(j*4)) + 00391 conv_integer(sum1_p((j*4)-1)) + 00392 conv_integer(sum1_p((j*4)-2)) + 00393 conv_integer(sum1_p((j*4)-3))),5); 00394 00395 if status1_n1((j*4)) = '1' then 00396 index_n1_latch3(j) <= "11"; 00397 index_n1_latch2(j) <= index_n1_latch(j*4); 00398 elsif status1_n1((j*4)-1) = '1' then 00399 index_n1_latch3(j) <= "10"; 00400 index_n1_latch2(j) <= index_n1_latch((j*4)-1); 00401 elsif status1_n1((j*4)-2) = '1' then 00402 index_n1_latch3(j) <= "01"; 00403 index_n1_latch2(j) <= index_n1_latch((j*4)-2); 00404 elsif status1_n1((j*4)-3) = '1' then 00405 index_n1_latch3(j) <= "00"; 00406 index_n1_latch2(j) <= index_n1_latch((j*4)-3); 00407 else 00408 status2_n1(j) <= '0'; 00409 index_n1_latch2(j) <= "00"; 00410 end if; 00411 00412 sum2_n(j) <= conv_std_logic_vector((conv_integer(sum1_n(j*4)) + 00413 conv_integer(sum1_n((j*4)-1)) + 00414 conv_integer(sum1_n((j*4)-2)) + 00415 conv_integer(sum1_n((j*4)-3))),5); 00416 00417 end loop; 00418 00419 ------------------------------- lower 4 bits 2nd edge ------------------------------------- 00420 b := dec13 (status11_p1(4 downto 2)); 00421 x := dec13 (status11_n1(4 downto 2)); 00422 00423 if status2_p1(2) = '0' then --no edge in top 4 bits, search for 2nd 00424 if (status11_p1(3) and status11_p1(4)) = '1' then 00425 index_p2_latch333(1 downto 0) := "10"; 00426 index_p2_out <= index_p_low(3); 00427 elsif (status11_p1(2) and 00428 (status11_p1(3) xor status11_p1(4))) = '1' then 00429 index_p2_latch333(1 downto 0) := "01"; 00430 index_p2_out <= index_p_low(2); 00431 elsif (status11_p1(1) and b) = '1' then 00432 index_p2_latch333(1 downto 0) := "00"; 00433 index_p2_out <= index_p_low(1); 00434 else 00435 status1_p2(1) <= '0'; 00436 index_p2_latch333(1 downto 0) := "00"; 00437 index_p2_out <= "00"; 00438 end if; 00439 elsif status2_p1(2) = '1' then -- 1 edge in top 4 bits, search for 1st 00440 if status11_p1(4) = '1' then 00441 index_p2_latch333(1 downto 0) := "11"; 00442 index_p2_out <= index_p_low(4); 00443 elsif status11_p1(3) = '1' then 00444 index_p2_latch333(1 downto 0) := "10"; 00445 index_p2_out <= index_p_low(3); 00446 elsif status11_p1(2) = '1' then 00447 index_p2_latch333(1 downto 0) := "01"; 00448 index_p2_out <= index_p_low(2); 00449 elsif status11_p1(1) = '1' then 00450 index_p2_latch333(1 downto 0) := "00"; 00451 index_p2_out <= index_p_low(1); 00452 else 00453 status1_p2(1) <= '0'; 00454 index_p2_latch333(1 downto 0) := "00"; 00455 index_p2_out <= "00"; 00456 end if; 00457 else 00458 status1_p2(1) <= '0'; 00459 index_p2_latch333(1 downto 0) := "00"; 00460 index_p2_out <= "00"; 00461 end if; 00462 index_p2_latch33 <= index_p2_latch333; 00463 00464 index_p2_latch33_1 <= index_p2_latch3; 00465 index_p2_out_1 <= index_p2_latch; 00466 00467 if status2_n1(2) = '0' then 00468 if (status11_n1(3) and status11_n1(4)) = '1' then 00469 index_n2_latch333(1 downto 0) := "10"; 00470 index_n2_out <= index_n_low(3); 00471 elsif (status11_n1(2) and 00472 (status11_n1(3) xor status11_n1(4))) = '1' then 00473 index_n2_latch333(1 downto 0) := "01"; 00474 index_n2_out <= index_n_low(2); 00475 elsif (status11_n1(1) and x) = '1' then 00476 index_n2_latch333(1 downto 0) := "00"; 00477 index_n2_out <= index_n_low(1); 00478 else 00479 status1_n2(1) <= '0'; 00480 index_n2_latch333(1 downto 0) := "00"; 00481 index_n2_out <= "00"; 00482 end if; 00483 elsif status2_n1(2) = '1' then 00484 if status11_n1(4) = '1' then 00485 index_n2_latch333(1 downto 0) := "11"; 00486 index_n2_out <= index_n_low(4); 00487 elsif status11_n1(3) = '1' then 00488 index_n2_latch333(1 downto 0) := "10"; 00489 index_n2_out <= index_n_low(3); 00490 elsif status11_n1(2) = '1' then 00491 index_n2_latch333(1 downto 0) := "01"; 00492 index_n2_out <= index_n_low(2); 00493 elsif status11_n1(1) = '1' then 00494 index_n2_latch333(1 downto 0) := "00"; 00495 index_n2_out <= index_n_low(1); 00496 else 00497 status1_n2(1) <= '0'; 00498 index_n2_latch333(1 downto 0) := "00"; 00499 index_n2_out <= "00"; 00500 end if; 00501 else 00502 status1_n2(1) <= '0'; 00503 index_n2_latch333(1 downto 0) := "00"; 00504 index_n2_out <= "00"; 00505 end if; 00506 index_n2_latch33 <= index_n2_latch333; 00507 00508 index_n2_latch33_1 <= index_n2_latch3; 00509 index_n2_out_1 <= index_n2_latch; 00510 00511 status1_p2(2) <= status12_p2; 00512 status1_n2(2) <= status12_n2; 00513 00514 --------------------------------- lower 4 bits 3rd edge ------------------------------------- 00515 m := dec23 (status11_p1(4 downto 2)); 00516 n := dec23 (status11_n1(4 downto 2)); 00517 00518 if status2_p1(2) = '1' then --1 edge in top 4 bits, search for 2nd 00519 if (status11_p1(3) and status11_p1(4)) = '1' then 00520 index_p3_latch333(1 downto 0) := "10"; 00521 index_p3_out <= index_p_low(3); 00522 elsif (status11_p1(2) and 00523 (status11_p1(3) xor status11_p1(4))) = '1' then 00524 index_p3_latch333(1 downto 0) := "01"; 00525 index_p3_out <= index_p_low(2); 00526 elsif (status11_p1(1) and b) = '1' then 00527 index_p3_latch333(1 downto 0) := "00"; 00528 index_p3_out <= index_p_low(1); 00529 else 00530 status1_p3(1) <= '0'; 00531 index_p3_latch333(1 downto 0) := "00"; 00532 index_p3_out <= "00"; 00533 end if; 00534 elsif status12_p2 = '1' then --2 edges in top 4 bits, search for 1st 00535 if status11_p1(4) = '1' then 00536 index_p3_latch333(1 downto 0) := "11"; 00537 index_p3_out <= index_p_low(4); 00538 elsif status11_p1(3) = '1' then 00539 index_p3_latch333(1 downto 0) := "10"; 00540 index_p3_out <= index_p_low(3); 00541 elsif status11_p1(2) = '1' then 00542 index_p3_latch333(1 downto 0) := "01"; 00543 index_p3_out <= index_p_low(2); 00544 elsif status11_p1(1) = '1' then 00545 index_p3_latch333(1 downto 0) := "00"; 00546 index_p3_out <= index_p_low(1); 00547 else 00548 status1_p3(1) <= '0'; 00549 index_p3_latch333(1 downto 0) := "00"; 00550 index_p3_out <= "00"; 00551 end if; 00552 else --no edges in top 4 bits, search for 3rd 00553 if (status11_p1(4) and status11_p1(3) and status11_p1(2)) = '1' then 00554 index_p3_latch333(1 downto 0) := "01"; 00555 index_p3_out <= index_p_low(2); 00556 elsif (m and status11_p1(1)) = '1' then 00557 index_p3_latch333(1 downto 0) := "00"; 00558 index_p3_out <= index_p_low(1); 00559 else 00560 status1_p3(1) <= '0'; 00561 index_p3_latch333(1 downto 0) := "00"; 00562 index_p3_out <= "00"; 00563 end if; 00564 end if; 00565 index_p3_latch33 <= index_p3_latch333; 00566 00567 index_p3_latch33_1 <= index_p3_latch3; 00568 index_p3_out_1 <= index_p3_latch; 00569 00570 if status2_n1(2) = '1' then --1 edge in top 4 bits, search for 2nd 00571 if (status11_n1(3) and status11_n1(4)) = '1' then 00572 index_n3_latch333(1 downto 0) := "10"; 00573 index_n3_out <= index_n_low(3); 00574 elsif (status11_n1(2) and 00575 (status11_n1(3) xor status11_n1(4))) = '1' then 00576 index_n3_latch333(1 downto 0) := "01"; 00577 index_n3_out <= index_n_low(2); 00578 elsif (status11_n1(1) and x) = '1' then 00579 index_n3_latch333(1 downto 0) := "00"; 00580 index_n3_out <= index_n_low(1); 00581 else 00582 status1_n3(1) <= '0'; 00583 index_n3_latch333(1 downto 0) := "00"; 00584 index_n3_out <= "00"; 00585 end if; 00586 elsif status12_n2 = '1' then --2 edges in top 4 bits, search for 1st 00587 if status11_n1(4) = '1' then 00588 index_n3_latch333(1 downto 0) := "11"; 00589 index_n3_out <= index_n_low(4); 00590 elsif status11_n1(3) = '1' then 00591 index_n3_latch333(1 downto 0) := "10"; 00592 index_n3_out <= index_n_low(3); 00593 elsif status11_n1(2) = '1' then 00594 index_n3_latch333(1 downto 0) := "01"; 00595 index_n3_out <= index_n_low(2); 00596 elsif status11_n1(1) = '1' then 00597 index_n3_latch333(1 downto 0) := "00"; 00598 index_n3_out <= index_n_low(1); 00599 else 00600 status1_n3(1) <= '0'; 00601 index_n3_latch333(1 downto 0) := "00"; 00602 index_n3_out <= "00"; 00603 end if; 00604 else --no edges in top 4 bits, search for 3rd 00605 if (status11_n1(4) and status11_n1(3) and status11_n1(2)) = '1' then 00606 index_n3_latch333(1 downto 0) := "01"; 00607 index_n3_out <= index_n_low(2); 00608 elsif (n and status11_p1(1)) = '1' then 00609 index_n3_latch333(1 downto 0) := "00"; 00610 index_n3_out <= index_n_low(1); 00611 else 00612 status1_n3(1) <= '0'; 00613 index_n3_latch333(1 downto 0) := "00"; 00614 index_n3_out <= "00"; 00615 end if; 00616 end if; 00617 index_n3_latch33 <= index_n3_latch333; 00618 00619 index_n3_latch33_1 <= index_n3_latch3; 00620 index_n3_out_1 <= index_n3_latch; 00621 00622 status1_p3(2) <= status12_p3; 00623 status1_n3(2) <= status12_n3; 00624 00625 ------------------------------- status, MSB pos1 ------------------------------------- 00626 if status2_p1(2) = '1' then --final status flag pos1 00627 index_p1_latch4 <= '1'; 00628 index_p1_latch22 <= index_p1_latch2(2); 00629 index_p1_latch33 <= index_p1_latch3(2); 00630 elsif status2_p1(1) = '1' then 00631 index_p1_latch4 <= '0'; 00632 index_p1_latch22 <= index_p1_latch2(1); 00633 index_p1_latch33 <= index_p1_latch3(1); 00634 else 00635 status_i_p1 <= '0'; 00636 index_p1_latch22 <= "00"; 00637 index_p1_latch33 <= "00"; 00638 index_p1_latch4 <= '0'; 00639 end if; 00640 00641 sum_p <= conv_std_logic_vector((conv_integer(sum2_p(1)) + conv_integer(sum2_p(2))), 6); 00642 00643 if status2_n1(2) = '1' then 00644 index_n1_latch4 <= '1'; 00645 index_n1_latch22 <= index_n1_latch2(2); 00646 index_n1_latch33 <= index_n1_latch3(2); 00647 elsif status2_n1(1) = '1' then 00648 index_n1_latch4 <= '0'; 00649 index_n1_latch22 <= index_n1_latch2(1); 00650 index_n1_latch33 <= index_n1_latch3(1); 00651 else 00652 status_i_n1 <= '0'; 00653 index_n1_latch22 <= "00"; 00654 index_n1_latch33 <= "00"; 00655 index_n1_latch4 <= '0'; 00656 end if; 00657 00658 sum_n <= conv_std_logic_vector((conv_integer(sum2_n(1)) + conv_integer(sum2_n(2))), 6); 00659 00660 ------------------------------- output assignments ------------------------------------- 00661 STATUS_P1_i <= status_i_p1; 00662 EDGE_RIS1_i <= index_p1_latch4 & index_p1_latch33 & index_p1_latch22; 00663 00664 STATUS_P2_i <= status1_p2(2) or status1_p2(1); 00665 if status1_p2(2) = '1' then -- take values from upper or lower half of status1 00666 EDGE_RIS2_i <= index_p2_latch33_1 & index_p2_out_1; 00667 else 00668 EDGE_RIS2_i <= '0' & index_p2_latch33 & index_p2_out; 00669 end if; 00670 00671 STATUS_P3_i <= status1_p3(2) or status1_p3(1); 00672 if status1_p3(2) = '1' then 00673 EDGE_RIS3_i <= index_p3_latch33_1 & index_p3_out_1; 00674 else 00675 EDGE_RIS3_i <= '0' & index_p3_latch33 & index_p3_out; 00676 end if; 00677 00678 SUM_RIS_i <= sum_p; 00679 00680 STATUS_N1_i <= status_i_n1; 00681 EDGE_FAL1_i <= index_n1_latch4 & index_n1_latch33 & index_n1_latch22; 00682 00683 STATUS_N2_i <= status1_n2(2) or status1_n2(1); 00684 if status1_n2(2) = '1' then 00685 EDGE_FAL2_i <= index_n2_latch33_1 & index_n2_out_1; 00686 else 00687 EDGE_FAL2_i <= '0' & index_n2_latch33 & index_n2_out; 00688 end if; 00689 00690 STATUS_N3_i <= status1_n3(2) or status1_n3(1); 00691 if status1_n3(2) = '1' then 00692 EDGE_FAL3_i <= index_n3_latch33_1 & index_n3_out_1; 00693 else 00694 EDGE_FAL3_i <= '0' & index_n3_latch33 & index_n3_out; 00695 end if; 00696 00697 SUM_FAL_i <= sum_n; 00698 00699 00700 SUM_RIS <= SUM_RIS_i; 00701 SUM_FAL <= SUM_FAL_i; 00702 00703 if STATUS_N2_i = '1' then 00704 if EDGE_RIS2_i < EDGE_RIS1_i then 00705 EDGE_FAL1 <= EDGE_RIS1_i+2; 00706 EDGE_FAL2 <= EDGE_RIS2_i+2; 00707 else 00708 EDGE_FAL1 <= EDGE_RIS2_i+2; 00709 EDGE_FAL2 <= EDGE_RIS1_i+2; 00710 end if; 00711 STATUS_P1 <= STATUS_N2_i; 00712 if STATUS_P2_i = '0' then 00713 STATUS_P2 <= '0'; 00714 else 00715 STATUS_P2 <= STATUS_N1_i; 00716 end if; 00717 00718 else 00719 00720 if STATUS_P1_i = '1' then 00721 EDGE_FAL1 <= EDGE_RIS1_i+2; 00722 STATUS_N1 <= STATUS_P1_i; 00723 else 00724 EDGE_FAL1 <= (others => '0'); 00725 STATUS_N1 <= '0'; 00726 end if; 00727 STATUS_N2 <= '0'; 00728 EDGE_FAL2 <= (others => '0'); 00729 00730 if STATUS_P2_i = '1' then 00731 STATUS_P1 <= '1'; 00732 else 00733 STATUS_P1 <= '0'; 00734 end if; 00735 00736 end if; 00737 00738 00739 if STATUS_P2_i = '1' then 00740 if EDGE_FAL2_i < EDGE_FAL1_i then 00741 EDGE_RIS1 <= EDGE_FAL1_i-1; 00742 EDGE_RIS2 <= EDGE_FAL2_i-1; 00743 else 00744 EDGE_RIS1 <= EDGE_FAL2_i-1; 00745 EDGE_RIS2 <= EDGE_FAL1_i-1; 00746 end if; 00747 STATUS_N1 <= STATUS_P2_i; 00748 if STATUS_N2_i = '0' then 00749 STATUS_N2 <= '0'; 00750 else 00751 STATUS_N2 <= STATUS_P1_i; 00752 end if; 00753 00754 else 00755 00756 if STATUS_N1_i = '1' then 00757 EDGE_RIS1 <= EDGE_FAL1_i-1; 00758 STATUS_P1 <= STATUS_N1_i; 00759 else 00760 EDGE_RIS1 <= (others => '0'); 00761 STATUS_P1 <= '0'; 00762 end if; 00763 STATUS_P2 <= '0'; 00764 EDGE_RIS2 <= (others => '0'); 00765 00766 if STATUS_N2_i = '0' then 00767 STATUS_N1 <= '1'; 00768 else 00769 STATUS_N1 <= '0'; 00770 end if; 00771 end if; 00772 00773 EDGE_FAL3 <= (others => '0'); 00774 EDGE_RIS3 <= (others => '0'); 00775 STATUS_P3 <= '0'; 00776 STATUS_N3 <= '0'; 00777 00778 end if; 00779 end process;
The documentation for this class was generated from the following file:
