shift_reg Entity Reference
Adjustable 32-bit wide shift register. More...
Inheritance diagram for shift_reg:
Collaboration diagram for shift_reg:
Architectures | |
| shift_reg_a | Architecture |
| DPBRAM instantiation. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| XilinxCoreLib | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
Ports | |
| addra | in std_logic_vector ( 7 downto 0 ) |
| Addr A. | |
| addrb | in std_logic_vector ( 7 downto 0 ) |
| Addr B. | |
| clka | in std_logic |
| Clk A. | |
| clkb | in std_logic |
| Clk B. | |
| dina | in std_logic_vector ( 31 downto 0 ) |
| Data in. | |
| doutb | out std_logic_vector ( 31 downto 0 ) |
| Data out. | |
| ena | in std_logic |
| Enable A. | |
| enb | in std_logic |
| Enable B. | |
| wea | in std_logic |
| Write enable. | |
Detailed Description
Adjustable 32-bit wide shift register.Adjustable 32-bit wide shift register built on DPBRAM block
Definition at line 70 of file shift_reg.vhd.
Member Data Documentation
addra in std_logic_vector ( 7 downto 0 ) [Port] |
addrb in std_logic_vector ( 7 downto 0 ) [Port] |
clka in std_logic [Port] |
clkb in std_logic [Port] |
dina in std_logic_vector ( 31 downto 0 ) [Port] |
doutb out std_logic_vector ( 31 downto 0 ) [Port] |
ena in std_logic [Port] |
enb in std_logic [Port] |
ieee library [Library] |
std_logic_1164 package [Package] |
wea in std_logic [Port] |
The documentation for this class was generated from the following file:
