status_collector Entity Reference

Data collector for DCS status messages. More...

Inheritance diagram for status_collector:

Inheritance graph
[legend]
Collaboration diagram for status_collector:

Collaboration graph
[legend]

List of all members.


Architectures

status_collector_arc Architecture
 Data collector for status messages. More...

Libraries

ieee 
 standard IEEE library
work 
 Library with project specific headers.

Packages

std_logic_1164 
 std_logic definitions, see file
std_logic_arith 
 arithmetic operations on std_logic datatypes, see file
std_logic_unsigned 
 unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
build_parameters  Package <build_parameters>
 Header with config parameters for building the project.

Ports

DEBUG  out std_logic_vector ( 14 downto 0 )
EMAC_CLK  in std_logic
 100 MHz
RATES_CLK  in std_logic
 40 MHz
STATUS_CLK  in std_logic
 200 MHz
RIO_CLK  in std_logic
 160 MHz
RESET  in std_logic
 Global Reset.
START  in std_logic
 Start assembling packet.
FETCH_BYTE  in std_logic
 Get data byte, hold high until TRANS_DONE = 1.
FETCH_CHKSUM  in std_logic
 Get checksum, set for 1 clk cycle.
ERROR_FLAG  in std_logic
 Error flag.
EXT_CLK_DET  in std_logic
 Extern clock status flag.
RIO_DAQ  in std_logic
 DAQ RocketIO status flag.
RIO_SATA  in std_logic
 SATA RocketIO status flag.
MODE  in std_logic
 Expert or normal mode.
DCM_STATUS  in std_logic
 DCM status flag.
ROD_STATUS  in std_logic
 ROD status flag.
FPGA_ID  in std_logic_vector ( 7 downto 0 ) := x " 00 "
 FPGA ID.
MAIN_FSM  in std_logic_vector ( 7 downto 0 )
 State of main FSM.
ERROR_CODE  in std_logic_vector ( 31 downto 0 )
 Error code.
DSS_CIBU_STATUS  in std_logic_vector ( 31 downto 0 )
 Status of DSS & CIBU outputs.
INPUT_STATUS  in std_logic_vector ( 63 downto 0 )
 Status of inputs, ie active or masked.
TDAQ_PARAMS  in std_logic_vector ( 159 downto 0 ) := ( others = > ' 0 ' )
 All TDAQ Parameters.
HITRATE_CH1  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch.
HITRATE_CH2  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch.
HITRATE_CH3  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch.
HITRATE_CH4  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch.
HITRATE_CH5  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch.
HITRATE_CH6  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch.
HITRATE_CH7  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch.
HITRATE_CH8  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch.
ALGO_STATE  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Algo State.
HITRATE_A_CH1  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo A.
HITRATE_A_CH2  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo A.
HITRATE_A_CH3  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo A.
HITRATE_A_CH4  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo A.
HITRATE_A_CH5  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo A.
HITRATE_A_CH6  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo A.
HITRATE_A_CH7  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo A.
HITRATE_A_CH8  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo A.
HITRATE_B_CH1  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo B.
HITRATE_B_CH2  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo B.
HITRATE_B_CH3  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo B.
HITRATE_B_CH4  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo B.
HITRATE_B_CH5  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo B.
HITRATE_B_CH6  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo B.
HITRATE_B_CH7  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo B.
HITRATE_B_CH8  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo B.
HITRATE_C_CH1  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo C.
HITRATE_C_CH2  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo C.
HITRATE_C_CH3  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo C.
HITRATE_C_CH4  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo C.
HITRATE_C_CH5  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo C.
HITRATE_C_CH6  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo C.
HITRATE_C_CH7  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo C.
HITRATE_C_CH8  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo C.
HITRATE_D_CH1  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo D.
HITRATE_D_CH2  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo D.
HITRATE_D_CH3  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo D.
HITRATE_D_CH4  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo D.
HITRATE_D_CH5  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo D.
HITRATE_D_CH6  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo D.
HITRATE_D_CH7  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo D.
HITRATE_D_CH8  in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
 Hit Rate 1 Ch Algo D.
ASM_DONE  out std_logic
 Packet assembly done, set FETCH_BYTE & FETCH_CHKSUM afterwards.
TRANS_DONE  out std_logic
 Transfer of full packet done.
CHKSUM_OUT  out std_logic_vector ( 15 downto 0 )
 Checksum out to EMAC.
DATA_OUT  out std_logic_vector ( 7 downto 0 )
 Data byte to EMAC.

Attributes

MAX_FANOUT  string
MAX_FANOUT  " 10 "


Detailed Description

Data collector for DCS status messages.

This entity collects all the data for the 1 Hz DCS status messages. It synchronizes all inputs from various clock domains to 100 MHz, puts them in the correct byte order & computes the UDP checksum. When everything is done an output flag is asserted.
The packet structure is outlined here

Definition at line 43 of file status_collector.vhd.


Member Data Documentation

ALGO_STATE in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Algo State.

Definition at line 76 of file status_collector.vhd.

ASM_DONE out std_logic [Port]

Packet assembly done, set FETCH_BYTE & FETCH_CHKSUM afterwards.

Definition at line 109 of file status_collector.vhd.

build_parameters package [Package]

Header with config parameters for building the project.

Definition at line 35 of file status_collector.vhd.

CHKSUM_OUT out std_logic_vector ( 15 downto 0 ) [Port]

Checksum out to EMAC.

Definition at line 111 of file status_collector.vhd.

DATA_OUT out std_logic_vector ( 7 downto 0 ) [Port]

Data byte to EMAC.

Definition at line 112 of file status_collector.vhd.

DCM_STATUS in std_logic [Port]

DCM status flag.

Definition at line 60 of file status_collector.vhd.

DSS_CIBU_STATUS in std_logic_vector ( 31 downto 0 ) [Port]

Status of DSS & CIBU outputs.

Definition at line 65 of file status_collector.vhd.

EMAC_CLK in std_logic [Port]

100 MHz

Definition at line 47 of file status_collector.vhd.

ERROR_CODE in std_logic_vector ( 31 downto 0 ) [Port]

Error code.

Definition at line 64 of file status_collector.vhd.

ERROR_FLAG in std_logic [Port]

Error flag.

Definition at line 55 of file status_collector.vhd.

EXT_CLK_DET in std_logic [Port]

Extern clock status flag.

Definition at line 56 of file status_collector.vhd.

FETCH_BYTE in std_logic [Port]

Get data byte, hold high until TRANS_DONE = 1.

Definition at line 53 of file status_collector.vhd.

FETCH_CHKSUM in std_logic [Port]

Get checksum, set for 1 clk cycle.

Definition at line 54 of file status_collector.vhd.

FPGA_ID in std_logic_vector ( 7 downto 0 ) := x " 00 " [Port]

FPGA ID.

Definition at line 62 of file status_collector.vhd.

HITRATE_A_CH1 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo A.

Definition at line 77 of file status_collector.vhd.

HITRATE_A_CH2 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo A.

Definition at line 78 of file status_collector.vhd.

HITRATE_A_CH3 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo A.

Definition at line 79 of file status_collector.vhd.

HITRATE_A_CH4 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo A.

Definition at line 80 of file status_collector.vhd.

HITRATE_A_CH5 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo A.

Definition at line 81 of file status_collector.vhd.

HITRATE_A_CH6 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo A.

Definition at line 82 of file status_collector.vhd.

HITRATE_A_CH7 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo A.

Definition at line 83 of file status_collector.vhd.

HITRATE_A_CH8 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo A.

Definition at line 84 of file status_collector.vhd.

HITRATE_B_CH1 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo B.

Definition at line 85 of file status_collector.vhd.

HITRATE_B_CH2 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo B.

Definition at line 86 of file status_collector.vhd.

HITRATE_B_CH3 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo B.

Definition at line 87 of file status_collector.vhd.

HITRATE_B_CH4 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo B.

Definition at line 88 of file status_collector.vhd.

HITRATE_B_CH5 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo B.

Definition at line 89 of file status_collector.vhd.

HITRATE_B_CH6 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo B.

Definition at line 90 of file status_collector.vhd.

HITRATE_B_CH7 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo B.

Definition at line 91 of file status_collector.vhd.

HITRATE_B_CH8 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo B.

Definition at line 92 of file status_collector.vhd.

HITRATE_C_CH1 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo C.

Definition at line 93 of file status_collector.vhd.

HITRATE_C_CH2 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo C.

Definition at line 94 of file status_collector.vhd.

HITRATE_C_CH3 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo C.

Definition at line 95 of file status_collector.vhd.

HITRATE_C_CH4 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo C.

Definition at line 96 of file status_collector.vhd.

HITRATE_C_CH5 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo C.

Definition at line 97 of file status_collector.vhd.

HITRATE_C_CH6 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo C.

Definition at line 98 of file status_collector.vhd.

HITRATE_C_CH7 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo C.

Definition at line 99 of file status_collector.vhd.

HITRATE_C_CH8 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo C.

Definition at line 100 of file status_collector.vhd.

HITRATE_CH1 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch.

Definition at line 68 of file status_collector.vhd.

HITRATE_CH2 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch.

Definition at line 69 of file status_collector.vhd.

HITRATE_CH3 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch.

Definition at line 70 of file status_collector.vhd.

HITRATE_CH4 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch.

Definition at line 71 of file status_collector.vhd.

HITRATE_CH5 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch.

Definition at line 72 of file status_collector.vhd.

HITRATE_CH6 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch.

Definition at line 73 of file status_collector.vhd.

HITRATE_CH7 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch.

Definition at line 74 of file status_collector.vhd.

HITRATE_CH8 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch.

Definition at line 75 of file status_collector.vhd.

HITRATE_D_CH1 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo D.

Definition at line 101 of file status_collector.vhd.

HITRATE_D_CH2 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo D.

Definition at line 102 of file status_collector.vhd.

HITRATE_D_CH3 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo D.

Definition at line 103 of file status_collector.vhd.

HITRATE_D_CH4 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo D.

Definition at line 104 of file status_collector.vhd.

HITRATE_D_CH5 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo D.

Definition at line 105 of file status_collector.vhd.

HITRATE_D_CH6 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo D.

Definition at line 106 of file status_collector.vhd.

HITRATE_D_CH7 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo D.

Definition at line 107 of file status_collector.vhd.

HITRATE_D_CH8 in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Port]

Hit Rate 1 Ch Algo D.

Definition at line 108 of file status_collector.vhd.

ieee library [Library]

standard IEEE library

Reimplemented in main_components.

Definition at line 25 of file status_collector.vhd.

INPUT_STATUS in std_logic_vector ( 63 downto 0 ) [Port]

Status of inputs, ie active or masked.

Definition at line 66 of file status_collector.vhd.

MAIN_FSM in std_logic_vector ( 7 downto 0 ) [Port]

State of main FSM.

Definition at line 63 of file status_collector.vhd.

MODE in std_logic [Port]

Expert or normal mode.

Definition at line 59 of file status_collector.vhd.

RATES_CLK in std_logic [Port]

40 MHz

Definition at line 48 of file status_collector.vhd.

RESET in std_logic [Port]

Global Reset.

Definition at line 51 of file status_collector.vhd.

RIO_CLK in std_logic [Port]

160 MHz

Definition at line 50 of file status_collector.vhd.

RIO_DAQ in std_logic [Port]

DAQ RocketIO status flag.

Definition at line 57 of file status_collector.vhd.

RIO_SATA in std_logic [Port]

SATA RocketIO status flag.

Definition at line 58 of file status_collector.vhd.

ROD_STATUS in std_logic [Port]

ROD status flag.

Definition at line 61 of file status_collector.vhd.

START in std_logic [Port]

Start assembling packet.

Definition at line 52 of file status_collector.vhd.

STATUS_CLK in std_logic [Port]

200 MHz

Definition at line 49 of file status_collector.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Reimplemented in main_components.

Definition at line 27 of file status_collector.vhd.

std_logic_arith package [Package]

arithmetic operations on std_logic datatypes, see file

Definition at line 29 of file status_collector.vhd.

std_logic_unsigned package [Package]

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

Definition at line 31 of file status_collector.vhd.

TDAQ_PARAMS in std_logic_vector ( 159 downto 0 ) := ( others = > ' 0 ' ) [Port]

All TDAQ Parameters.

Definition at line 67 of file status_collector.vhd.

TRANS_DONE out std_logic [Port]

Transfer of full packet done.

Definition at line 110 of file status_collector.vhd.

work library [Library]

Library with project specific headers.

Definition at line 33 of file status_collector.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 01:00:18 2008 for BCM-AAA by doxygen 1.5.7.1-20081012