ddr2_mem_top_0.arc_top Architecture Reference
Top module of DDR2 RAM controller. More...
Inheritance diagram for ddr2_mem_top_0.arc_top:
Collaboration diagram for ddr2_mem_top_0.arc_top:
Components | |
| ddr2_mem_data_path_0 | <Entity ddr2_mem_data_path_0> |
| datapath | |
| ddr2_mem_iobs_0 | <Entity ddr2_mem_iobs_0> |
| IOBs. | |
| ddr2_mem_user_interface_0 | <Entity ddr2_mem_user_interface_0> |
| User interface. | |
| ddr2_mem_ddr2_controller_0 | <Entity ddr2_mem_ddr2_controller_0> |
| RAM controller. | |
Signals | |
| wr_df_data | std_logic_vector ( dq_width *2-1 downto 0 ) |
| mask_df_data | std_logic_vector ( dm_width *2-1 downto 0 ) |
| rd_data_rise | std_logic_vector ( data_width-1 downto 0 ) |
| rd_data_fall | std_logic_vector ( data_width-1 downto 0 ) |
| af_empty_w | std_logic |
| dq_tap_sel_done | std_logic |
| af_addr | std_logic_vector ( 35 downto 0 ) |
| ctrl_af_rden | std_logic |
| ctrl_wr_df_rden | std_logic |
| ctrl_dummy_rden | std_logic |
| ctrl_dqs_enable | std_logic |
| ctrl_dqs_reset | std_logic |
| ctrl_wr_en | std_logic |
| ctrl_rden | std_logic |
| dqs_idelay_inc | std_logic_vector ( ReadEnable-1 downto 0 ) |
| dqs_idelay_ce | std_logic_vector ( ReadEnable-1 downto 0 ) |
| dqs_idelay_rst | std_logic_vector ( ReadEnable-1 downto 0 ) |
| data_idelay_inc | std_logic_vector ( ReadEnable-1 downto 0 ) |
| data_idelay_ce | std_logic_vector ( ReadEnable-1 downto 0 ) |
| data_idelay_rst | std_logic_vector ( ReadEnable-1 downto 0 ) |
| dqs_rst | std_logic |
| dqs_en | std_logic |
| wr_en | std_logic |
| wr_data_rise | std_logic_vector ( ( data_width-1 ) downto 0 ) |
| wr_data_fall | std_logic_vector ( ( data_width-1 ) downto 0 ) |
| dqs_delayed | std_logic_vector ( ( data_strobe_width-1 ) downto 0 ) |
| mask_data_rise | std_logic_vector ( data_mask_width-1 downto 0 ) |
| mask_data_fall | std_logic_vector ( data_mask_width-1 downto 0 ) |
| ctrl_ddr2_address | std_logic_vector ( row_address-1 downto 0 ) |
| ctrl_ddr2_ba | std_logic_vector ( bank_address-1 downto 0 ) |
| ctrl_ddr2_ras_L | std_logic |
| ctrl_ddr2_cas_L | std_logic |
| ctrl_ddr2_we_L | std_logic |
| ctrl_ddr2_cs_L | std_logic |
| ctrl_ddr2_cke | std_logic |
| ctrl_ddr2_odt | std_logic |
| DDR2_DM_r | std_logic_vector ( data_mask_width-1 downto 0 ) |
| ctrl_dummy_wr_sel | std_logic |
| COMP_DONE | std_logic |
| dummy_write_flag | std_logic |
Component Instantiations | |
| data_path_00 | ddr2_mem_data_path_0 <Entity ddr2_mem_data_path_0> |
| Datapath. | |
| iobs_00 | ddr2_mem_iobs_0 <Entity ddr2_mem_iobs_0> |
| IOBs. | |
| user_interface_00 | ddr2_mem_user_interface_0 <Entity ddr2_mem_user_interface_0> |
| User interface. | |
| ddr2_controller_00 | ddr2_mem_ddr2_controller_0 <Entity ddr2_mem_ddr2_controller_0> |
| RAM controller. | |
Detailed Description
Top module of DDR2 RAM controller.This module instantiates the main design logic of memory interface and interfaces with the user.
Definition at line 102 of file ddr2_mem_top_0.vhd.
Member Data Documentation
data_path_00 ddr2_mem_data_path_0 [Component Instantiation] |
ddr2_controller_00 ddr2_mem_ddr2_controller_0 [Component Instantiation] |
ddr2_mem_data_path_0 [Component] |
ddr2_mem_ddr2_controller_0 [Component] |
ddr2_mem_iobs_0 [Component] |
ddr2_mem_user_interface_0 [Component] |
iobs_00 ddr2_mem_iobs_0 [Component Instantiation] |
user_interface_00 ddr2_mem_user_interface_0 [Component Instantiation] |
The documentation for this class was generated from the following file:
