lvl1_buf Entity Reference
Buffer for Level-1 TDAQ data.
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List of all members.
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Architectures |
| lvl1_buf_arc | Architecture |
| | Buffer for Level-1 TDAQ data. More...
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Libraries |
| ieee | |
| | standard IEEE library
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| unisim | |
| | Library with Xilinx primitives.
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Packages |
| std_logic_1164 | |
| | std_logic definitions, see file
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| std_logic_arith | |
| | arithmetic operations on std_logic datatypes, see file
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| std_logic_unsigned | |
| | unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
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| numeric_std | |
| | arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
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| vcomponents | |
| | Header with Xilinx primitives.
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Ports |
| RESET | in |
| | Reset.
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| CLKWR | in |
| | Clock for write, 40 MHz.
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| CLKRD | in |
| | Clock for read, 40 MHz.
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| DATA_OUT | out ( 191 downto 0 ) := ( others = > ' 0 ' ) |
| | Data out, including BID.
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| DATA_IN | in ( 175 downto 0 ) |
| | Data in.
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| WR_BID | in ( 11 downto 0 ) := " 000000000000 " |
| | BID of data to be written to buffer.
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| RD_BID | in ( 11 downto 0 ) := " 000000000000 " |
| | BID to be fetched from buffer.
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| VLD | out |
| | Valid for Data out; after EN_B goes high, no further rds will be accepted til VLD went high.
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| EN_B | in |
| | enable read, keep high til VLD is asserted high
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| NUM | in ( 6 downto 0 ) := " 0000001 " |
| | Number of bunches to be read per trigger.
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| FINISH | in |
| | abort transmission
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| all_READ | out |
| | flag signaling the specified number of bunches has been read
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| PAUSE | in |
| | Pause read-out when ROD is busy.
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| READ_ERROR | out |
| | Flag that an error has occurred.
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| WE | in |
| | Write enable.
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Detailed Description
Buffer for Level-1 TDAQ data.
This entity contains the circular buffer for the Level-1 TDAQ data. It is 500 bunch-crossings deep. Together with the data the current Bunch ID is also written to the buffer. For each read the ID of the bunch to be read needs to be provided so the buffer support logic can verify that the correct data has been read.
Definition at line 44 of file lvl1_buf.vhd.
Member Data Documentation
flag signaling the specified number of bunches has been read
Definition at line 56 of file lvl1_buf.vhd.
DATA_OUT out ( 191 downto 0 ) := ( others = > ' 0 ' ) [Port] |
enable read, keep high til VLD is asserted high
Definition at line 53 of file lvl1_buf.vhd.
NUM in ( 6 downto 0 ) := " 0000001 " [Port] |
Number of bunches to be read per trigger.
Definition at line 54 of file lvl1_buf.vhd.
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 32 of file lvl1_buf.vhd.
RD_BID in ( 11 downto 0 ) := " 000000000000 " [Port] |
BID to be fetched from buffer.
Definition at line 51 of file lvl1_buf.vhd.
Flag that an error has occurred.
Definition at line 58 of file lvl1_buf.vhd.
arithmetic operations on std_logic datatypes, see file
Definition at line 28 of file lvl1_buf.vhd.
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 30 of file lvl1_buf.vhd.
Library with Xilinx primitives.
Definition at line 34 of file lvl1_buf.vhd.
Header with Xilinx primitives.
Definition at line 36 of file lvl1_buf.vhd.
Valid for Data out; after EN_B goes high, no further rds will be accepted til VLD went high.
Definition at line 52 of file lvl1_buf.vhd.
WR_BID in ( 11 downto 0 ) := " 000000000000 " [Port] |
BID of data to be written to buffer.
Definition at line 50 of file lvl1_buf.vhd.
The documentation for this class was generated from the following file:
