bcm_rod_ram Entity Reference
DPRAM wrapper. More...
Inheritance diagram for bcm_rod_ram:
Collaboration diagram for bcm_rod_ram:
Architectures | |
| bcm_rod_ram_arc | Architecture |
| DPRAM wrapper with RAM support logic. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
Ports | |
| CLK | in std_logic |
| clock | |
| CLK_2X | in std_logic |
| 2x clock | |
| SCLR | in std_logic |
| synchronous reset | |
| data_input | in std_logic_vector ( 31 downto 0 ) |
| data in | |
| data_input_valid | in std_logic |
| data in valid | |
| data_input_endoffrag | in std_logic |
| end of fragment flag in | |
| stop | in std_logic |
| disable modue | |
| data_output_next | in std_logic |
| get next data blob out | |
| data_output | out std_logic_vector ( 31 downto 0 ) |
| data out | |
| data_output_vld | out std_logic |
| data out valid | |
| data_output_available | out std_logic |
| data out available flag | |
| data_output_endoffrag | out std_logic |
| end of fragment flag out | |
| busy | out std_logic |
| busy flag | |
| write_error | out std_logic |
| write error flag | |
| read_error | out std_logic |
| read error flag | |
Detailed Description
DPRAM wrapper.Dual Port circular RAM to buffer SLINK output
Definition at line 34 of file bcm_rod_ram.vhd.
Member Data Documentation
busy out std_logic [Port] |
CLK in std_logic [Port] |
CLK_2X in std_logic [Port] |
data_input in std_logic_vector ( 31 downto 0 ) [Port] |
data_input_endoffrag in std_logic [Port] |
data_input_valid in std_logic [Port] |
data_output out std_logic_vector ( 31 downto 0 ) [Port] |
data_output_available out std_logic [Port] |
data_output_endoffrag out std_logic [Port] |
data_output_next in std_logic [Port] |
data_output_vld out std_logic [Port] |
ieee library [Library] |
read_error out std_logic [Port] |
SCLR in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic_arith package [Package] |
arithmetic operations on std_logic datatypes, see file
Definition at line 28 of file bcm_rod_ram.vhd.
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 30 of file bcm_rod_ram.vhd.
stop in std_logic [Port] |
write_error out std_logic [Port] |
The documentation for this class was generated from the following file:
