ddr2_mem_top_0 Entity Reference
Top module of DDR2 RAM controller. More...
Inheritance diagram for ddr2_mem_top_0:
Collaboration diagram for ddr2_mem_top_0:
Architectures | |
| arc_top | Architecture |
| Top module of DDR2 RAM controller. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| work | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| ddr2_mem_parameters_0 | Package <ddr2_mem_parameters_0> |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| clk_0 | in std_logic |
| Clock. | |
| clk_90 | in std_logic |
| Clock. | |
| clk_50 | in std_logic |
| Clock. | |
| ref_clk | in std_logic |
| Clock. | |
| sys_rst | in std_logic |
| Reset. | |
| sys_rst90 | in std_logic |
| Reset. | |
| sys_rst_ref_clk_1 | in std_logic |
| Reset clock. | |
| DDR2_RESET_N | out std_logic |
| Reset. | |
| idelay_ctrl_rdy | in std_logic |
| iDelay ready flag | |
| DDR2_RAS_N | out std_logic |
| RAS. | |
| DDR2_CAS_N | out std_logic |
| CAS. | |
| DDR2_WE_N | out std_logic |
| Write enable. | |
| DDR2_ODT | out std_logic |
| On-Die Termination. | |
| DDR2_CKE | out std_logic |
| Clock enab;e. | |
| DDR2_CS_N | out std_logic |
| Chip Select. | |
| DDR2_DQ | inout std_logic_vector ( data_width-1 downto 0 ) |
| Data. | |
| DDR2_DQS | inout std_logic_vector ( data_strobe_width-1 downto 0 ) |
| Data Strobe pos. | |
| DDR2_DQS_N | inout std_logic_vector ( data_strobe_width-1 downto 0 ) |
| Data Strobe neg. | |
| DDR2_DM | out std_logic_vector ( data_mask_width-1 downto 0 ) |
| Data mask. | |
| DDR2_CK | out std_logic |
| diff clock pos | |
| DDR2_CK_N | out std_logic |
| diff clock neg | |
| DDR2_BA | out std_logic_vector ( bank_address-1 downto 0 ) |
| Bank address. | |
| DDR2_A | out std_logic_vector ( row_address-1 downto 0 ) |
| Address. | |
| WDF_ALMOST_FULL | out std_logic |
| data FIFO full flag | |
| AF_ALMOST_FULL | out std_logic |
| address FIFO full flag | |
| BURST_LENGTH | out std_logic_vector ( 2 downto 0 ) |
| Burst length. | |
| READ_DATA_VALID | out std_logic |
| READ_DATA_FIFO_OUT valid flag | |
| READ_DATA_FIFO_OUT | out std_logic_vector ( dq_width *2-1 downto 0 ) |
| data out | |
| APP_AF_ADDR | in std_logic_vector ( 35 downto 0 ) |
| Address in. | |
| APP_AF_WREN | in std_logic |
| address write enable | |
| APP_WDF_DATA | in std_logic_vector ( dq_width *2-1 downto 0 ) |
| data in | |
| APP_MASK_DATA | in std_logic_vector ( dm_width *2-1 downto 0 ) |
| data mask in | |
| APP_WDF_WREN | in std_logic |
| data write enable | |
| CLK_TB | out std_logic |
| clock for support logic | |
| RESET_TB | out std_logic |
| reset for support logic | |
Detailed Description
Top module of DDR2 RAM controller.This module instantiates the main design logic of memory interface and interfaces with the user.
Definition at line 59 of file ddr2_mem_top_0.vhd.
Member Data Documentation
AF_ALMOST_FULL out std_logic [Port] |
APP_AF_ADDR in std_logic_vector ( 35 downto 0 ) [Port] |
APP_AF_WREN in std_logic [Port] |
APP_MASK_DATA in std_logic_vector ( dm_width *2-1 downto 0 ) [Port] |
APP_WDF_DATA in std_logic_vector ( dq_width *2-1 downto 0 ) [Port] |
APP_WDF_WREN in std_logic [Port] |
BURST_LENGTH out std_logic_vector ( 2 downto 0 ) [Port] |
clk_0 in std_logic [Port] |
clk_50 in std_logic [Port] |
clk_90 in std_logic [Port] |
CLK_TB out std_logic [Port] |
DDR2_A out std_logic_vector ( row_address-1 downto 0 ) [Port] |
DDR2_BA out std_logic_vector ( bank_address-1 downto 0 ) [Port] |
DDR2_CAS_N out std_logic [Port] |
DDR2_CK out std_logic [Port] |
DDR2_CK_N out std_logic [Port] |
DDR2_CKE out std_logic [Port] |
DDR2_CS_N out std_logic [Port] |
DDR2_DM out std_logic_vector ( data_mask_width-1 downto 0 ) [Port] |
DDR2_DQ inout std_logic_vector ( data_width-1 downto 0 ) [Port] |
DDR2_DQS inout std_logic_vector ( data_strobe_width-1 downto 0 ) [Port] |
DDR2_DQS_N inout std_logic_vector ( data_strobe_width-1 downto 0 ) [Port] |
DDR2_ODT out std_logic [Port] |
DDR2_RAS_N out std_logic [Port] |
DDR2_RESET_N out std_logic [Port] |
DDR2_WE_N out std_logic [Port] |
idelay_ctrl_rdy in std_logic [Port] |
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 48 of file ddr2_mem_top_0.vhd.
READ_DATA_FIFO_OUT out std_logic_vector ( dq_width *2-1 downto 0 ) [Port] |
READ_DATA_VALID out std_logic [Port] |
ref_clk in std_logic [Port] |
RESET_TB out std_logic [Port] |
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 46 of file ddr2_mem_top_0.vhd.
sys_rst in std_logic [Port] |
sys_rst90 in std_logic [Port] |
sys_rst_ref_clk_1 in std_logic [Port] |
unisim library [Library] |
vcomponents package [Package] |
WDF_ALMOST_FULL out std_logic [Port] |
The documentation for this class was generated from the following file:
