xtemac Entity Reference

Virtex-4 FX Ethernet MAC Wrapper. More...

Inheritance diagram for xtemac:

Inheritance graph
[legend]
Collaboration diagram for xtemac:

Collaboration graph
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List of all members.


Architectures

WRAPPER Architecture
 EMAC Wrapper. More...

Libraries

unisim 
 Library with Xilinx primitives.
ieee 
 standard IEEE library

Packages

vcomponents 
 Header with Xilinx primitives.
std_logic_1164 
 std_logic definitions, see file

Ports

EMAC0CLIENTRXCLIENTCLKOUT  out std_logic
CLIENTEMAC0RXCLIENTCLKIN  in std_logic
EMAC0CLIENTRXD  out std_logic_vector ( 7 downto 0 )
EMAC0CLIENTRXDVLD  out std_logic
EMAC0CLIENTRXDVLDMSW  out std_logic
EMAC0CLIENTRXGOODFRAME  out std_logic
EMAC0CLIENTRXBADFRAME  out std_logic
EMAC0CLIENTRXFRAMEDROP  out std_logic
EMAC0CLIENTRXDVREG6  out std_logic
EMAC0CLIENTRXSTATS  out std_logic_vector ( 6 downto 0 )
EMAC0CLIENTRXSTATSVLD  out std_logic
EMAC0CLIENTRXSTATSBYTEVLD  out std_logic
EMAC0CLIENTTXCLIENTCLKOUT  out std_logic
CLIENTEMAC0TXCLIENTCLKIN  in std_logic
CLIENTEMAC0TXD  in std_logic_vector ( 7 downto 0 )
CLIENTEMAC0TXDVLD  in std_logic
CLIENTEMAC0TXDVLDMSW  in std_logic
EMAC0CLIENTTXACK  out std_logic
CLIENTEMAC0TXFIRSTBYTE  in std_logic
CLIENTEMAC0TXUNDERRUN  in std_logic
EMAC0CLIENTTXCOLLISION  out std_logic
EMAC0CLIENTTXRETRANSMIT  out std_logic
CLIENTEMAC0TXIFGDELAY  in std_logic_vector ( 7 downto 0 )
EMAC0CLIENTTXSTATS  out std_logic
EMAC0CLIENTTXSTATSVLD  out std_logic
EMAC0CLIENTTXSTATSBYTEVLD  out std_logic
CLIENTEMAC0PAUSEREQ  in std_logic
CLIENTEMAC0PAUSEVAL  in std_logic_vector ( 15 downto 0 )
GTX_CLK_0  in std_logic
EMAC0CLIENTTXGMIIMIICLKOUT  out std_logic
CLIENTEMAC0TXGMIIMIICLKIN  in std_logic
GMII_TXD_0  out std_logic_vector ( 7 downto 0 )
GMII_TX_EN_0  out std_logic
GMII_TX_ER_0  out std_logic
GMII_TX_CLK_0  out std_logic
GMII_RXD_0  in std_logic_vector ( 7 downto 0 )
GMII_RX_DV_0  in std_logic
GMII_RX_ER_0  in std_logic
GMII_RX_CLK_0  in std_logic
MII_TX_CLK_0  in std_logic
GMII_COL_0  in std_logic
GMII_CRS_0  in std_logic
MDC_0  out std_logic
MDIO_IN_0  in std_logic
MDIO_OUT_0  out std_logic
MDIO_TRI_0  out std_logic
HOSTCLK  in std_logic
RESET  in std_logic


Detailed Description

Virtex-4 FX Ethernet MAC Wrapper.

This is the top level VHDL wrapper for the Virtex-4 FX Ethernet MAC

Definition at line 81 of file temac.vhd.


Member Data Documentation

ieee library [Library]

standard IEEE library

Definition at line 72 of file temac.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Definition at line 74 of file temac.vhd.

unisim library [Library]

Library with Xilinx primitives.

Definition at line 67 of file temac.vhd.

vcomponents package [Package]

Header with Xilinx primitives.

Definition at line 69 of file temac.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 01:00:41 2008 for BCM-AAA by doxygen 1.5.7.1-20081012