ddr2_mem_controller_iobs_0 Entity Reference
Control signal IOBs. More...
Inheritance diagram for ddr2_mem_controller_iobs_0:
Collaboration diagram for ddr2_mem_controller_iobs_0:
Architectures | |
| arc_controller_iobs | Architecture |
| Control signal IOBs. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| work | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| ddr2_mem_parameters_0 | Package <ddr2_mem_parameters_0> |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| ctrl_ddr2_address | in std_logic_vector ( row_address-1 downto 0 ) |
| ctrl_ddr2_ba | in std_logic_vector ( bank_address-1 downto 0 ) |
| ctrl_ddr2_ras_L | in std_logic |
| ctrl_ddr2_cas_L | in std_logic |
| ctrl_ddr2_we_L | in std_logic |
| ctrl_ddr2_cs_L | in std_logic |
| ctrl_ddr2_cke | in std_logic |
| ctrl_ddr2_odt | in std_logic |
| DDR_ADDRESS | out std_logic_vector ( row_address-1 downto 0 ) |
| DDR_BA | out std_logic_vector ( bank_address-1 downto 0 ) |
| DDR_RAS_L | out std_logic |
| DDR_CAS_L | out std_logic |
| DDR_WE_L | out std_logic |
| DDR_ODT | out std_logic |
| DDR_CKE | out std_logic |
| DDR_CS_L | out std_logic |
Detailed Description
Control signal IOBs.This module puts the memory control signals like address, bank address, row address strobe, column address strobe, write enable and clock enable in the IOBs.
Definition at line 63 of file ddr2_mem_controller_iobs_0.vhd.
Member Data Documentation
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 49 of file ddr2_mem_controller_iobs_0.vhd.
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 47 of file ddr2_mem_controller_iobs_0.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
