eth_buf.eth_buf_arc Architecture Reference

address generation for buffer More...

Inheritance diagram for eth_buf.eth_buf_arc:

[legend]

Collaboration diagram for eth_buf.eth_buf_arc:

[legend]

List of all members.

Processes
wr_addr	( CLK_WR )
	write address generation
rd_addr	( CLK_RD )
	write address generation
Components
ethbuf	<Entity ethbuf>
	DPRAM.
Signals
a_i	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
b_i	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
Component Instantiations
bram_buf	ethbuf <Entity ethbuf>

---

Detailed Description

address generation for buffer

Definition at line 51 of file eth_buf.vhd.

---

Member Function Documentation

[Process]

rd_addr

( CLK_RD )

write address generation

Definition at line 93 of file eth_buf.vhd.

  rd_addr : process(CLK_RD)
  begin
    if CLK_RD'event and CLK_RD = '1' then
      if RES = '1' then
        a_i <= (others => '0');
      else
        if RD = '1' then
          if a_i = 383 then
            a_i <= (others => '0');
          else
            a_i <= a_i + 1;
          end if;
        else
          a_i <= a_i;
        end if;
      end if;
    end if;
  end process rd_addr;

[Process]

wr_addr

( CLK_WR )

write address generation

Definition at line 73 of file eth_buf.vhd.

  wr_addr : process(CLK_WR)
  begin
    if CLK_WR'event and CLK_WR = '1' then
      if RES = '1' then
        b_i <= conv_std_logic_vector(12, 5);
      else
        if WR = '1' then
          if b_i = 23 then
            b_i <= (others => '0');
          else
            b_i <= b_i + 1;
          end if;
        else
          b_i <= b_i;
        end if;
      end if;
    end if;
  end process wr_addr;

---

Member Data Documentation

ethbuf [Component]

DPRAM.

Definition at line 57 of file eth_buf.vhd.

---

The documentation for this class was generated from the following file:

• eth_buf.vhd