ddr2_mem_rd_wr_addr_fifo_0 Entity Reference

FIFO for read/write address. More...

Inheritance diagram for ddr2_mem_rd_wr_addr_fifo_0:

Collaboration diagram for ddr2_mem_rd_wr_addr_fifo_0:

List of all members.

Architectures

arc_rd_wr_addr_fifo Architecture

FIFO for read/write address. More...

Libraries

ieee

standard IEEE library

work

unisim

Library with Xilinx primitives.

Packages

std_logic_1164

std_logic definitions, see file

std_logic_unsigned

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

ddr2_mem_parameters_0 Package <ddr2_mem_parameters_0>

vcomponents

Header with Xilinx primitives.

Ports

clk0 in std_logic

clk90 in std_logic

rst in std_logic

app_af_addr in std_logic_vector ( 35 downto 0 )

app_af_WrEn in std_logic

ctrl_af_RdEn in std_logic

af_addr out std_logic_vector ( 35 downto 0 )

af_Empty out std_logic

af_Almost_full out std_logic

Detailed Description

FIFO for read/write address.

This module instantiates the block RAM based FIFO to store the user address and the command information.

ieee library [Library]

standard IEEE library

std_logic_1164 package [Package]

std_logic definitions, see file

std_logic_unsigned package [Package]

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

unisim library [Library]

Library with Xilinx primitives.

vcomponents package [Package]

Header with Xilinx primitives.

The documentation for this class was generated from the following file:


Architectures
arc_rd_wr_addr_fifo	Architecture
	FIFO for read/write address. More...
Libraries
ieee
	standard IEEE library
work
unisim
	Library with Xilinx primitives.
Packages
std_logic_1164
	std_logic definitions, see file
std_logic_unsigned
	unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
ddr2_mem_parameters_0	Package <ddr2_mem_parameters_0>
vcomponents
	Header with Xilinx primitives.
Ports
clk0	in std_logic
clk90	in std_logic
rst	in std_logic
app_af_addr	in std_logic_vector ( 35 downto 0 )
app_af_WrEn	in std_logic
ctrl_af_RdEn	in std_logic
af_addr	out std_logic_vector ( 35 downto 0 )
af_Empty	out std_logic
af_Almost_full	out std_logic