lvl1_buf.lvl1_buf_arc Architecture Reference

Buffer for Level-1 TDAQ data. More...

Inheritance diagram for lvl1_buf.lvl1_buf_arc:

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Collaboration diagram for lvl1_buf.lvl1_buf_arc:

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List of all members.

Processes
addr_gen_a	( CLKWR )
	Cyclic addressing of write half.
rd_ram	( CLKRD )
	reading from ram
fwd_data	( CLKRD )
	forward data to outs
latch_more2	( CLKRD , RESET )
	latch enable for more BCs
latch_block	( CLKRD , RESET )
	latch enable for more BCs
Components
lvl1_circ_buffer	<Entity lvl1_circ_buffer>
	Circular Buffer, DP-RAM as a BRAM Core.
Signals
data_i	std_logic_vector ( 191 downto 0 ) := ( others = > ' 0 ' )
data_out_i	std_logic_vector ( 191 downto 0 ) := ( others = > ' 0 ' )
cnt_a	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
cnt_b	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
bid_lastin	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
bid_lastram	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
num_i	std_logic_vector ( 6 downto 0 ) := " 0000001 "
rden	std_logic := ' 0 '
check	std_logic := ' 0 '
rden_ram	std_logic := ' 0 '
more	std_logic := ' 0 '
more2	std_logic := ' 0 '
allr	std_logic := ' 0 '
nblock	std_logic := ' 1 '
vld_i	std_logic := ' 0 '
Component Instantiations
buf_i	lvl1_circ_buffer <Entity lvl1_circ_buffer>
	Circular Buffer, DP-RAM as a BRAM Core.

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Detailed Description

Buffer for Level-1 TDAQ data.

This entity contains the circular buffer for the Level-1 TDAQ data. It is 500 bunch-crossings deep. Together with the data the current Bunch ID is also written to the buffer. For each read the ID of the bunch to be read needs to be provided so the buffer support logic can verify that the correct data has been read.

Definition at line 69 of file lvl1_buf.vhd.

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Member Function Documentation

[Process]

addr_gen_a

( CLKWR )

Cyclic addressing of write half.

Definition at line 125 of file lvl1_buf.vhd.

  addr_gen_a : process(CLKWR)
  begin
    if CLKWR'event and CLKWR = '1' then
      if RESET = '1' then
        cnt_a       <= (others => '0');
        data_i      <= (others => '0');
        bid_lastram <= (others => '0');
        bid_lastin  <= (others => '0');
      else
        if WE = '1' then
          cnt_a      <= WR_BID;         --* store last wr BID
          data_i     <= WR_BID & DATA_IN & "0000";
          bid_lastin <= WR_BID;
          if WR_BID = 0 then
            bid_lastram <= bid_lastin;
          else
            bid_lastram <= bid_lastram;
          end if;
        end if;
      end if;
    end if;
  end process addr_gen_a;

[Process]

fwd_data

( CLKRD )

forward data to outs

Definition at line 196 of file lvl1_buf.vhd.

  fwd_data : process (CLKRD)
  begin  -- process fwd_data
    if CLKRD'event and CLKRD = '1' then  -- rising clock edge
      if RESET = '1' then
        allr     <= '0';
        vld_i    <= '0';
        DATA_OUT <= (others => '0');
      else
        if PAUSE = '0' then
          
          if check = '1' then
            DATA_OUT <= data_out_i;
            vld_i    <= '1';
            if more2 = '0' then
              allr <= '1';
            else
              allr <= '0';
            end if;
            
          else
            allr     <= '0';
            vld_i    <= '0';
            DATA_OUT <= (others => '0');
          end if;
          
        else
          allr     <= '0';
          vld_i    <= '0';
          DATA_OUT <= (others => '0');
        end if;
        
      end if;
    end if;
  end process fwd_data;

[Process]

latch_block		( CLKRD ,
		RESET )

latch enable for more BCs

Definition at line 246 of file lvl1_buf.vhd.

  latch_block : process (CLKRD, RESET)
  begin  -- process latch_more
    if RESET = '1' then                     -- asynchronous reset (active high)
      nblock <= '1';
    elsif CLKRD'event and CLKRD = '1' then  -- rising clock edge
      if vld_i = '1' then
        nblock <= '1';
      elsif rden = '1' then
        nblock <= '0';
      end if;
    end if;
  end process latch_block;

[Process]

latch_more2		( CLKRD ,
		RESET )

latch enable for more BCs

Definition at line 232 of file lvl1_buf.vhd.

  latch_more2 : process (CLKRD, RESET)
  begin  -- process latch_more
    if RESET = '1' then                     -- asynchronous reset (active high)
      more2 <= '0';
    elsif CLKRD'event and CLKRD = '1' then  -- rising clock edge
      if (num_i-1) = 0 or FINISH = '1' then
        more2 <= '0';
      elsif more = '1' then
        more2 <= '1';
      end if;
    end if;
  end process latch_more2;

[Process]

rd_ram

( CLKRD )

reading from ram

Definition at line 149 of file lvl1_buf.vhd.

  rd_ram : process(CLKRD)
  begin
    if CLKRD'event and CLKRD = '1' then
      if RESET = '1' then
        cnt_b    <= (others => '0');
        rden_ram <= '0';
        more     <= '0';
      else
        if PAUSE = '0' then
          
          if EN_B = '1' then
            cnt_b    <= RD_BID;
            rden_ram <= '1';
            num_i    <= NUM;

            if NUM > 1 then
              more <= '1';
            else
              more <= '0';
            end if;
            
          elsif (more2 and nblock and (not rden_ram)) = '1' then
            rden_ram <= '1';
            num_i    <= num_i - 1;
            cnt_b    <= cnt_b + 1;
            if cnt_b = bid_lastram and bid_lastram > 0 then
              cnt_b <= (others => '0');
            end if;
            
          else
            cnt_b    <= cnt_b;
            rden_ram <= '0';
            more     <= '0';
          end if;
          
        else
          cnt_b    <= cnt_b;
          rden_ram <= '0';
        end if;
      end if;
    end if;
  end process;

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Member Data Documentation

buf_i lvl1_circ_buffer [Component Instantiation]

Circular Buffer, DP-RAM as a BRAM Core.

Definition at line 110 of file lvl1_buf.vhd.

lvl1_circ_buffer [Component]

Circular Buffer, DP-RAM as a BRAM Core.

Definition at line 89 of file lvl1_buf.vhd.

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The documentation for this class was generated from the following file:

• lvl1_buf.vhd