Processes | |
PROCESS_30 | ( CLK_IN ) |
counter for frequency division | |
Signals | |
clock_out_i | std_logic := ' 0 ' |
counter_i | integer range 0 to 127 := INITIAL_VALUE |
Definition at line 45 of file clock_divider.vhd.
PROCESS_30 | ( CLK_IN ) |
counter for frequency division
Definition at line 53 of file clock_divider.vhd.
00053 process (CLK_IN) 00054 begin 00055 if (CLK_IN'event and CLK_IN = '1') then 00056 if (counter_i = 2) then 00057 clock_out_i <= not clock_out_i; 00058 counter_i <= DIVISION_FACTOR; 00059 else 00060 counter_i <= counter_i - 2; 00061 end if; 00062 end if; 00063 end process;