ddr2_mem_data_write_0.arc_data_write Architecture Reference

Write data organizer. More...

Inheritance diagram for ddr2_mem_data_write_0.arc_data_write:

Collaboration diagram for ddr2_mem_data_write_0.arc_data_write:

List of all members.

Processes

PROCESS_36 ( CLK90 )

PROCESS_37 ( CLK )

PROCESS_38 ( CLK90 )

PROCESS_39 ( CLK90 )

Signals

dqs_rst_r1 std_logic

dqs_rst_r2 std_logic

dqs_en_r1 std_logic

dqs_en_r2 std_logic

dqs_en_r3 std_logic

wr_en_clk270_r1 std_logic

wr_en_clk90_r3 std_logic

dummy_rise_pattern std_logic_vector ( dq_width-1 downto 0 )

dummy_fall_pattern std_logic_vector ( dq_width-1 downto 0 )

dummy_flag std_logic

CTRL_DUMMY_WR_SEL_270 std_logic

CTRL_DUMMY_WR_SEL_90 std_logic

CTRL_DUMMY_WR_SEL_r1 std_logic

patA std_logic_vector ( 143 downto 0 )

pat5 std_logic_vector ( 143 downto 0 )

pat9 std_logic_vector ( 143 downto 0 )

pat6 std_logic_vector ( 143 downto 0 )

Detailed Description

Write data organizer.

This module splits the user data into the rise data and the fall data.

Definition at line 84 of file ddr2_mem_data_write_0.vhd.

The documentation for this class was generated from the following file:


Processes
PROCESS_36	( CLK90 )
PROCESS_37	( CLK )
PROCESS_38	( CLK90 )
PROCESS_39	( CLK90 )
Signals
dqs_rst_r1	std_logic
dqs_rst_r2	std_logic
dqs_en_r1	std_logic
dqs_en_r2	std_logic
dqs_en_r3	std_logic
wr_en_clk270_r1	std_logic
wr_en_clk90_r3	std_logic
dummy_rise_pattern	std_logic_vector ( dq_width-1 downto 0 )
dummy_fall_pattern	std_logic_vector ( dq_width-1 downto 0 )
dummy_flag	std_logic
CTRL_DUMMY_WR_SEL_270	std_logic
CTRL_DUMMY_WR_SEL_90	std_logic
CTRL_DUMMY_WR_SEL_r1	std_logic
patA	std_logic_vector ( 143 downto 0 )
pat5	std_logic_vector ( 143 downto 0 )
pat9	std_logic_vector ( 143 downto 0 )
pat6	std_logic_vector ( 143 downto 0 )