ddr2_mem_pattern_compare8 Entity Reference

DDR2 pattern compare. More...

Inheritance diagram for ddr2_mem_pattern_compare8:

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Collaboration diagram for ddr2_mem_pattern_compare8:

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List of all members.


Architectures

arc_pattern_compare Architecture
 DDR2 pattern compare. More...

Libraries

ieee 
 standard IEEE library

Packages

std_logic_1164 
 std_logic definitions, see file
std_logic_unsigned 
 unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
numeric_std 
 arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file

Ports

clk  in std_logic
 clock
rst  in std_logic
 reset
ctrl_rden  in std_logic
 read enable
rd_data_rise  in std_logic_vector ( 7 downto 0 )
 rising edge data
rd_data_fall  in std_logic_vector ( 7 downto 0 )
 falling edge data
comp_done  out std_logic
 done flag
first_rising  out std_logic
 start flag
rd_en_rise  out std_logic
 read enable rising edge data
rd_en_fall  out std_logic
 read enable falling edge data


Detailed Description

DDR2 pattern compare.

Compares the IOB output 8 bit data of one bank that is read data during the intilaization to get the delay for the data with respect to the command issued.

Definition at line 53 of file ddr2_mem_pattern_compare8.vhd.


Member Data Documentation

clk in std_logic [Port]

clock

Definition at line 55 of file ddr2_mem_pattern_compare8.vhd.

comp_done out std_logic [Port]

done flag

Definition at line 60 of file ddr2_mem_pattern_compare8.vhd.

ctrl_rden in std_logic [Port]

read enable

Definition at line 57 of file ddr2_mem_pattern_compare8.vhd.

first_rising out std_logic [Port]

start flag

Definition at line 61 of file ddr2_mem_pattern_compare8.vhd.

ieee library [Library]

standard IEEE library

Definition at line 41 of file ddr2_mem_pattern_compare8.vhd.

numeric_std package [Package]

arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file

Definition at line 47 of file ddr2_mem_pattern_compare8.vhd.

rd_data_fall in std_logic_vector ( 7 downto 0 ) [Port]

falling edge data

Definition at line 59 of file ddr2_mem_pattern_compare8.vhd.

rd_data_rise in std_logic_vector ( 7 downto 0 ) [Port]

rising edge data

Definition at line 58 of file ddr2_mem_pattern_compare8.vhd.

rd_en_fall out std_logic [Port]

read enable falling edge data

Definition at line 63 of file ddr2_mem_pattern_compare8.vhd.

rd_en_rise out std_logic [Port]

read enable rising edge data

Definition at line 62 of file ddr2_mem_pattern_compare8.vhd.

rst in std_logic [Port]

reset

Definition at line 56 of file ddr2_mem_pattern_compare8.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Definition at line 43 of file ddr2_mem_pattern_compare8.vhd.

std_logic_unsigned package [Package]

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

Definition at line 45 of file ddr2_mem_pattern_compare8.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 00:50:20 2008 for BCM-AAA by doxygen 1.5.7.1-20081012