ddr2_mem_wr_data_fifo_16.arc_wr_data_fifo_16 Architecture Reference

Write data FIFO. More...

Inheritance diagram for ddr2_mem_wr_data_fifo_16.arc_wr_data_fifo_16:

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Collaboration diagram for ddr2_mem_wr_data_fifo_16.arc_wr_data_fifo_16:

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List of all members.

Processes
PROCESS_165	( clk90 )
	read enable sync
PROCESS_166	( clk90 )
	read enable sync
Components
FIFO16
	FIFO primitive.
Signals
ctrl_Wdf_RdEn_270	std_logic
ctrl_Wdf_RdEn_90	std_logic
Component Instantiations
Wdf_1	FIFO16
	address FIFO

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Detailed Description

Write data FIFO.

This module instantiates the block RAM based FIFO to store the user interface data into it and read after a specified amount in already written. The reading starts when the almost full signal is generated whose offset is programmable.

Definition at line 78 of file ddr2_mem_wr_data_fifo_16.vhd.

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Member Function Documentation

[Process]

PROCESS_165

( clk90 )

read enable sync

Definition at line 115 of file ddr2_mem_wr_data_fifo_16.vhd.

  process(clk90)
  begin
    if clk90'event and clk90 = '0' then
      ctrl_Wdf_RdEn_270 <= ctrl_Wdf_RdEn;
    end if;
  end process;

[Process]

PROCESS_166

( clk90 )

read enable sync

Definition at line 123 of file ddr2_mem_wr_data_fifo_16.vhd.

  process(clk90)
  begin
    if clk90'event and clk90 = '1' then
      ctrl_Wdf_RdEn_90 <= ctrl_Wdf_RdEn_270;
    end if;
  end process;

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Member Data Documentation

FIFO16 [Component]

FIFO primitive.

Definition at line 81 of file ddr2_mem_wr_data_fifo_16.vhd.

Wdf_1 FIFO16 [Component Instantiation]

address FIFO

Definition at line 131 of file ddr2_mem_wr_data_fifo_16.vhd.

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The documentation for this class was generated from the following file:

• ddr2_mem_wr_data_fifo_16.vhd