Processes | |
cnt_rds | ( CLK ) |
Counter. | |
Signals | |
cnt | std_logic_vector ( 22 downto 0 ) := ( others = > ' 0 ' ) |
done_i | std_logic := ' 0 ' |
Definition at line 48 of file cnt_ddr_rd.vhd.
cnt_rds | ( CLK ) |
Counter.
Definition at line 58 of file cnt_ddr_rd.vhd.
00058 cnt_rds : process(CLK) 00059 begin 00060 if CLK'event and CLK = '1' then 00061 if RESET = '1' then 00062 cnt <= (others => '0'); 00063 done_i <= '0'; 00064 else 00065 if cnt = "11111111111111111111111" then 00066 done_i <= '1'; 00067 cnt <= (others => '0'); 00068 else 00069 done_i <= '0'; 00070 end if; 00071 if (EN = '1' and done_i = '0') then 00072 cnt <= cnt + 1; 00073 else 00074 cnt <= cnt; 00075 end if; 00076 end if; 00077 end if; 00078 end process cnt_rds;