ddr2_mem_tap_logic_0 Entity Reference
Data tap module. More...
Inheritance diagram for ddr2_mem_tap_logic_0:
Collaboration diagram for ddr2_mem_tap_logic_0:
Architectures | |
| arc_tap_logic | Architecture |
| Data tap module. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| work | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| ddr2_mem_parameters_0 | Package <ddr2_mem_parameters_0> |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CLK | in std_logic |
| clock | |
| CAL_CLK | in std_logic |
| calibration clock | |
| RESET0 | in std_logic |
| reset | |
| RESET_CAL_CLK | in std_logic |
| calibration reset | |
| CTRL_DUMMYREAD_START | in std_logic |
| start of calibration | |
| idelay_ctrl_rdy | in std_logic |
| iDelay ready flag | |
| dqs_delayed | in std_logic_vector ( data_strobe_width-1 downto 0 ) |
| delayed data strobe | |
| data_idelay_inc | out std_logic_vector ( readenable-1 downto 0 ) |
| iDelay increment | |
| data_idelay_ce | out std_logic_vector ( readenable-1 downto 0 ) |
| iDelay clock enable | |
| data_idelay_rst | out std_logic_vector ( readenable-1 downto 0 ) |
| iDelay reset | |
| dqs_idelay_inc | out std_logic_vector ( readenable-1 downto 0 ) |
| iDelay increment | |
| dqs_idelay_ce | out std_logic_vector ( readenable-1 downto 0 ) |
| iDelay clock enable | |
| dqs_idelay_rst | out std_logic_vector ( readenable-1 downto 0 ) |
| iDelay reset | |
| SEL_DONE | out std_logic |
| done flag | |
Detailed Description
Data tap module.This module instantiates the tap_cntrl and the data_tap_inc modules. Used for calibration of the memory data with the FPGA clock.
Definition at line 61 of file ddr2_mem_tap_logic_0.vhd.
Member Data Documentation
CAL_CLK in std_logic [Port] |
CLK in std_logic [Port] |
CTRL_DUMMYREAD_START in std_logic [Port] |
data_idelay_ce out std_logic_vector ( readenable-1 downto 0 ) [Port] |
data_idelay_inc out std_logic_vector ( readenable-1 downto 0 ) [Port] |
data_idelay_rst out std_logic_vector ( readenable-1 downto 0 ) [Port] |
dqs_delayed in std_logic_vector ( data_strobe_width-1 downto 0 ) [Port] |
dqs_idelay_ce out std_logic_vector ( readenable-1 downto 0 ) [Port] |
dqs_idelay_inc out std_logic_vector ( readenable-1 downto 0 ) [Port] |
dqs_idelay_rst out std_logic_vector ( readenable-1 downto 0 ) [Port] |
idelay_ctrl_rdy in std_logic [Port] |
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 48 of file ddr2_mem_tap_logic_0.vhd.
RESET0 in std_logic [Port] |
RESET_CAL_CLK in std_logic [Port] |
SEL_DONE out std_logic [Port] |
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 46 of file ddr2_mem_tap_logic_0.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
