delay_adj Entity Reference
Fine
delay for 2 RocketIO channels.
More...
List of all members.
|
Architectures |
| delay_adj_arc | Architecture |
| | Fine delay for 2 RocketIO channels. More...
|
Libraries |
| ieee | |
| | standard IEEE library
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Packages |
| std_logic_1164 | |
| | std_logic definitions, see file
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| std_logic_arith | |
| | arithmetic operations on std_logic datatypes, see file
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| std_logic_unsigned | |
| | unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
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Ports |
| CLK | in |
| | Clock.
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| A | in ( 31 downto 0 ) |
| | Data in ch1.
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| B | in ( 31 downto 0 ) |
| | Data in ch2.
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| X | out ( 31 downto 0 ) |
| | Shifted data ch1.
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| Y | out ( 31 downto 0 ) |
| | Shifted data ch2.
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| ADJ_TIME_1 | in range 0 to 32 |
| | Delay value ch1.
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| ADJ_TIME_2 | in range 0 to 32 |
| | Delay value ch1.
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Detailed Description
Fine
delay for 2 RocketIO channels.
Data can be shifted by taps, latency is 1 clock cycle. Delay value can be set at runtime.
Definition at line 35 of file delay_adj.vhd.
Member Data Documentation
A in ( 31 downto 0 ) [Port] |
B in ( 31 downto 0 ) [Port] |
arithmetic operations on std_logic datatypes, see file
Definition at line 28 of file delay_adj.vhd.
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 30 of file delay_adj.vhd.
X out ( 31 downto 0 ) [Port] |
Y out ( 31 downto 0 ) [Port] |
The documentation for this class was generated from the following file:
