ddr_eth_buf.ddr_eth_buf_arc Architecture Reference
Buffer between DDR & EMAC. More...
Inheritance diagram for ddr_eth_buf.ddr_eth_buf_arc:
Collaboration diagram for ddr_eth_buf.ddr_eth_buf_arc:
Processes | |
| wr_addr | ( CLK_WR ) |
| write address generation | |
| rd_addr | ( CLK_RD ) |
| read address generation | |
Components | |
| ddreth_buf | <Entity ddreth_buf> |
| DPRAM buffer. | |
Signals | |
| a_i | std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' ) |
| b_i | std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' ) |
Component Instantiations | |
| bram_buf | ddreth_buf <Entity ddreth_buf> |
| DPRAM buffer. | |
Detailed Description
Buffer between DDR & EMAC.Buffer between DDR & EMAC for clock domain crossing
Definition at line 54 of file ddr_eth_buf.vhd.
Member Function Documentation
| rd_addr | ( CLK_RD ) |
read address generation
Definition at line 96 of file ddr_eth_buf.vhd.
00096 rd_addr : process(CLK_RD) 00097 begin 00098 if CLK_RD'event and CLK_RD = '1' then 00099 if RES = '1' then 00100 a_i <= (others => '0'); 00101 else 00102 if RD = '1' then 00103 if a_i = 383 then 00104 a_i <= (others => '0'); 00105 else 00106 a_i <= a_i + 1; 00107 end if; 00108 else 00109 a_i <= a_i; 00110 end if; 00111 end if; 00112 end if; 00113 end process rd_addr;
| wr_addr | ( CLK_WR ) |
write address generation
Definition at line 76 of file ddr_eth_buf.vhd.
00076 wr_addr : process(CLK_WR) 00077 begin 00078 if CLK_WR'event and CLK_WR = '1' then 00079 if RES = '1' then 00080 b_i <= conv_std_logic_vector(24, 6); 00081 else 00082 if WR = '1' then 00083 if b_i = 47 then 00084 b_i <= (others => '0'); 00085 else 00086 b_i <= b_i + 1; 00087 end if; 00088 else 00089 b_i <= b_i; 00090 end if; 00091 end if; 00092 end if; 00093 end process wr_addr;
Member Data Documentation
bram_buf ddreth_buf [Component Instantiation] |
ddreth_buf [Component] |
The documentation for this class was generated from the following file:
