ddr2_mem_data_path_0.arc_data_path Architecture Reference

Calibration structure for data. More...

Inheritance diagram for ddr2_mem_data_path_0.arc_data_path:

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Collaboration diagram for ddr2_mem_data_path_0.arc_data_path:

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List of all members.

Components
ddr2_mem_data_write_0	<Entity ddr2_mem_data_write_0>
	Write data module.
ddr2_mem_tap_logic_0	<Entity ddr2_mem_tap_logic_0>
	Tap Logic.
Component Instantiations
data_write_10	ddr2_mem_data_write_0 <Entity ddr2_mem_data_write_0>
	Write data module.
tap_logic_00	ddr2_mem_tap_logic_0 <Entity ddr2_mem_tap_logic_0>
	Tap Logic.

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Detailed Description

Calibration structure for data.

This module instantiates the tap logic and the data write modules. Gives the rise and the fall data and the calibration information for the IDELAY elements.

Definition at line 102 of file ddr2_mem_data_path_0.vhd.

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Member Data Documentation

data_write_10 ddr2_mem_data_write_0 [Component Instantiation]

Write data module.

Definition at line 150 of file ddr2_mem_data_path_0.vhd.

ddr2_mem_data_write_0 [Component]

Write data module.

Definition at line 105 of file ddr2_mem_data_path_0.vhd.

ddr2_mem_tap_logic_0 [Component]

Tap Logic.

Definition at line 128 of file ddr2_mem_data_path_0.vhd.

tap_logic_00 ddr2_mem_tap_logic_0 [Component Instantiation]

Tap Logic.

Definition at line 172 of file ddr2_mem_data_path_0.vhd.

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The documentation for this class was generated from the following file:

• ddr2_mem_data_path_0.vhd