edge_det Entity Reference
Data edge detection. More...
Architectures | |
| new2 | Architecture |
| Data edge detection. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| work | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| daq_header | Package <daq_header> |
Ports | |
| DATA_IN | in std_logic_vector ( 31 downto 0 ) |
| raw data in | |
| CLK | in std_logic |
| clock | |
| SUM_RIS | out std_logic_vector ( 5 downto 0 ) |
| multiplicity rising | |
| SUM_FAL | out std_logic_vector ( 5 downto 0 ) |
| multiplicity falling | |
| EDGE_RIS1 | out std_logic_vector ( 4 downto 0 ) |
| position 1st edge rising | |
| EDGE_RIS2 | out std_logic_vector ( 4 downto 0 ) |
| position 2nd edge rising | |
| EDGE_RIS3 | out std_logic_vector ( 4 downto 0 ) |
| position 3rd edge rising | |
| EDGE_FAL1 | out std_logic_vector ( 4 downto 0 ) |
| position 1st edge falling | |
| EDGE_FAL2 | out std_logic_vector ( 4 downto 0 ) |
| position 2nd edge falling | |
| EDGE_FAL3 | out std_logic_vector ( 4 downto 0 ) |
| position 3rd edge falling | |
| STATUS_P1 | out std_logic |
| valid flag 1st rising | |
| STATUS_P2 | out std_logic |
| valid flag 2nd rising | |
| STATUS_P3 | out std_logic |
| valid flag 3rd rising | |
| STATUS_N1 | out std_logic |
| valid flag 1st falling | |
| STATUS_N2 | out std_logic |
| valid flag 2nd falling | |
| STATUS_N3 | out std_logic |
| valid flag 3rd falling | |
Detailed Description
Data edge detection.
This entity checks the 32bit vector of one RocketIO channel for edges, determines if it's rising or falling and returns those indices in binary. Up to 3 rising and falling edges can be detected. Latency is 6 clock cycles, with one dummy latch inserted for easier alignment with the bunch clock.
Also the multiplicity per edge is determined. Detailed information can be found in these documents: document
Definition at line 45 of file edge_det.vhd.
Member Data Documentation
CLK in std_logic [Port] |
DATA_IN in std_logic_vector ( 31 downto 0 ) [Port] |
EDGE_FAL1 out std_logic_vector ( 4 downto 0 ) [Port] |
EDGE_FAL2 out std_logic_vector ( 4 downto 0 ) [Port] |
EDGE_FAL3 out std_logic_vector ( 4 downto 0 ) [Port] |
EDGE_RIS1 out std_logic_vector ( 4 downto 0 ) [Port] |
EDGE_RIS2 out std_logic_vector ( 4 downto 0 ) [Port] |
EDGE_RIS3 out std_logic_vector ( 4 downto 0 ) [Port] |
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 33 of file edge_det.vhd.
STATUS_N1 out std_logic [Port] |
STATUS_N2 out std_logic [Port] |
STATUS_N3 out std_logic [Port] |
STATUS_P1 out std_logic [Port] |
STATUS_P2 out std_logic [Port] |
STATUS_P3 out std_logic [Port] |
std_logic_1164 package [Package] |
std_logic_arith package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 31 of file edge_det.vhd.
SUM_FAL out std_logic_vector ( 5 downto 0 ) [Port] |
SUM_RIS out std_logic_vector ( 5 downto 0 ) [Port] |
The documentation for this class was generated from the following file:
