ddr2_mem_v4_dqs_iob Entity Reference
DDR2 data strobe IOBs. More...
Inheritance diagram for ddr2_mem_v4_dqs_iob:
Collaboration diagram for ddr2_mem_v4_dqs_iob:
Architectures | |
| arc_v4_dqs_iob | Architecture |
| DDR2 data strobe IOBs. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CLK | in std_logic |
| clock | |
| CAL_CLK | in std_logic |
| calibration clock | |
| RESET | in std_logic |
| reset | |
| DLYINC | in std_logic |
| delay increment | |
| DLYCE | in std_logic |
| delay clock enable | |
| DLYRST | in std_logic |
| delay reset | |
| CTRL_DQS_RST | in std_logic |
| delay control reset | |
| CTRL_DQS_EN | in std_logic |
| delay control enable | |
| DDR_DQS | inout std_logic |
| DDR data strobe. | |
| DDR_DQS_L | inout std_logic |
| DDR data strobe. | |
| DQS_RISE | out std_logic |
| rising edge data strobe | |
Detailed Description
DDR2 data strobe IOBs.This module places the data stobes in the IOBs.
Definition at line 56 of file ddr2_mem_v4_dqs_iob.vhd.
Member Data Documentation
CAL_CLK in std_logic [Port] |
CLK in std_logic [Port] |
CTRL_DQS_EN in std_logic [Port] |
CTRL_DQS_RST in std_logic [Port] |
DDR_DQS inout std_logic [Port] |
DDR_DQS_L inout std_logic [Port] |
DLYCE in std_logic [Port] |
DLYINC in std_logic [Port] |
DLYRST in std_logic [Port] |
DQS_RISE out std_logic [Port] |
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 48 of file ddr2_mem_v4_dqs_iob.vhd.
RESET in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 46 of file ddr2_mem_v4_dqs_iob.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
