Processes | |
PROCESS_325 | ( CLK ) |
main adder logic | |
Signals | |
propagate | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
gen_carry | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
result | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
carry | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
carry_in | std_logic := ' 0 ' |
Definition at line 53 of file onescomplementadder.vhd.
PROCESS_325 | ( clk ) |
main adder logic
Definition at line 73 of file onescomplementadder.vhd.
00073 process(clk) 00074 variable x : std_logic := '0'; 00075 begin 00076 if clk'event and clk = '1' then 00077 if RESET = '1' then 00078 result <= (others => '0'); 00079 carry <= (others => '0'); 00080 else 00081 if EN = '1' then 00082 if C_IN = '1' then 00083 result(0) <= A(0) xnor B(0); 00084 carry(0) <= A (0) or B(0); 00085 else 00086 result(0) <= A(0) xor B(0); 00087 carry(0) <= A(0) and B(0); 00088 end if; 00089 for i in 15 downto 1 loop 00090 if gen_carry(i-1) = '1' then 00091 result(i) <= A(i) xnor B(i); 00092 carry(i) <= A(i) or B(i); 00093 elsif propagate(i-1) = '1' then 00094 for j in (i-1) downto 0 loop 00095 if gen_carry(j) = '1' then 00096 x := '1'; 00097 exit; 00098 elsif propagate(j) = '0' then 00099 x := '0'; 00100 exit; 00101 else 00102 x := '0'; 00103 end if; 00104 end loop; 00105 result(i) <= (A(i) xor B(i)) xor x; 00106 carry(i) <= (A(i) and B(i)) or (A(i) and x) or (B(i) and x); 00107 else 00108 result(i) <= A(i) xor B(i); 00109 carry(i) <= A(i) and B(i); 00110 end if; 00111 end loop; 00112 end if; 00113 end if; 00114 end if; 00115 end process;