ddr2_mem_iobs_0 Entity Reference
DDR2 IOBs. More...
Inheritance diagram for ddr2_mem_iobs_0:
Collaboration diagram for ddr2_mem_iobs_0:
Architectures | |
| arc_iobs | Architecture |
| DDR2 IOBs. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| work | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| ddr2_mem_parameters_0 | Package <ddr2_mem_parameters_0> |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CLK | in std_logic |
| CLK90 | in std_logic |
| DDR_CK | out std_logic |
| DDR_CK_N | out std_logic |
| CAL_CLK | in std_logic |
| RESET0 | in std_logic |
| RESET90 | in std_logic |
| dqs_idelay_inc | in std_logic_vector ( readenable-1 downto 0 ) |
| dqs_idelay_ce | in std_logic_vector ( readenable-1 downto 0 ) |
| dqs_idelay_rst | in std_logic_vector ( readenable-1 downto 0 ) |
| dqs_rst | in std_logic |
| dqs_en | in std_logic |
| wr_en | in std_logic |
| dqs_delayed | out std_logic_vector ( data_strobe_width-1 downto 0 ) |
| data_idelay_inc | in std_logic_vector ( readenable-1 downto 0 ) |
| data_idelay_ce | in std_logic_vector ( readenable-1 downto 0 ) |
| data_idelay_rst | in std_logic_vector ( readenable-1 downto 0 ) |
| wr_data_rise | in std_logic_vector ( data_width-1 downto 0 ) |
| wr_data_fall | in std_logic_vector ( data_width-1 downto 0 ) |
| mask_data_rise | in std_logic_vector ( data_mask_width-1 downto 0 ) |
| mask_data_fall | in std_logic_vector ( data_mask_width-1 downto 0 ) |
| rd_data_rise | out std_logic_vector ( data_width-1 downto 0 ) |
| rd_data_fall | out std_logic_vector ( data_width-1 downto 0 ) |
| DDR_DQ | inout std_logic_vector ( data_width-1 downto 0 ) |
| DDR_DQS | inout std_logic_vector ( data_strobe_width-1 downto 0 ) |
| DDR_DQS_L | inout std_logic_vector ( data_strobe_width-1 downto 0 ) |
| DDR_DM | out std_logic_vector ( data_mask_width-1 downto 0 ) |
| DDR_ADDRESS | out std_logic_vector ( row_address-1 downto 0 ) |
| DDR_BA | out std_logic_vector ( bank_address-1 downto 0 ) |
| DDR_RAS_L | out std_logic |
| DDR_CAS_L | out std_logic |
| DDR_WE_L | out std_logic |
| DDR_cs_L | out std_logic |
| DDR_CKE | out std_logic |
| DDR_ODT | out std_logic |
| ctrl_ddr2_ras_L | in std_logic |
| ctrl_ddr2_cas_L | in std_logic |
| ctrl_ddr2_we_L | in std_logic |
| ctrl_ddr2_odt | in std_logic |
| ctrl_ddr2_cke | in std_logic |
| ctrl_ddr2_cs_L | in std_logic |
| ctrl_ddr2_ba | in std_logic_vector ( bank_address-1 downto 0 ) |
| ctrl_ddr2_address | in std_logic_vector ( row_address-1 downto 0 ) |
Detailed Description
DDR2 IOBs.This module instantiates all the iobs modules. It is the interface between the main logic and the memory.
Definition at line 61 of file ddr2_mem_iobs_0.vhd.
Member Data Documentation
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 48 of file ddr2_mem_iobs_0.vhd.
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 46 of file ddr2_mem_iobs_0.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
