delta_t_ac_top.one_to_one Architecture Reference

1-1 Coincidence within time window More...

Inheritance diagram for delta_t_ac_top.one_to_one:

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Collaboration diagram for delta_t_ac_top.one_to_one:

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List of all members.

Processes
select_for_each	( clk5x )
	2-to-1 decoder for each channel
Components
ADDSUB48	<Entity ADDSUB48>
	Virtex-4 DSP Core.
comparator4	<Entity comparator4>
	custom 4-input comparator core
Signals
clk5x	std_logic := ' 0 '
hit_irena1	std_logic := ' 0 '
hit_ewa1	std_logic := ' 0 '
hit_heinz1	std_logic := ' 0 '
hit_andrej1	std_logic := ' 0 '
hit_marko1	std_logic := ' 0 '
hit_william1	std_logic := ' 0 '
hit_harris1	std_logic := ' 0 '
hit_helmut1	std_logic := ' 0 '
hit_irena	std_logic := ' 0 '
hit_ewa	std_logic := ' 0 '
hit_heinz	std_logic := ' 0 '
hit_andrej	std_logic := ' 0 '
hit_marko	std_logic := ' 0 '
hit_william	std_logic := ' 0 '
hit_harris	std_logic := ' 0 '
hit_helmut	std_logic := ' 0 '
hit_irena2	std_logic := ' 0 '
hit_ewa2	std_logic := ' 0 '
hit_heinz2	std_logic := ' 0 '
hit_andrej2	std_logic := ' 0 '
hit_marko2	std_logic := ' 0 '
hit_william2	std_logic := ' 0 '
hit_harris2	std_logic := ' 0 '
hit_helmut2	std_logic := ' 0 '
coin_flag_i	std_logic := ' 0 '
coin_flaga_i	std_logic := ' 0 '
coin_flagc_i	std_logic := ' 0 '
hitch11_i	std_logic_vector ( 2 downto 0 ) := " 000 "
hitch21_i	std_logic_vector ( 2 downto 0 ) := " 000 "
side_a_i	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
side_c_i	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
side_a1_i	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
side_c1_i	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
irena_int	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
ewa_int	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
heinz_int	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
andrej_int	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
marko_int	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
william_int	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
harris_int	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
helmut_int	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
irena1_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ewa1_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
heinz1_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
andrej1_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
marko1_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
william1_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
harris1_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
helmut1_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
irena1_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
ewa1_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
heinz1_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
andrej1_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
marko1_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
william1_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
harris1_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
helmut1_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
irena2_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ewa2_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
heinz2_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
andrej2_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
marko2_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
william2_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
harris2_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
helmut2_i	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
irena2_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
ewa2_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
heinz2_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
andrej2_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
marko2_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
william2_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
harris2_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
helmut2_xy	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
result_i	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
Component Instantiations
SideC	comparator4 <Entity comparator4>
SideA	comparator4 <Entity comparator4>
delta	ADDSUB48 <Entity ADDSUB48>

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Detailed Description

1-1 Coincidence within time window

This architecture applies a time window to each data input and if a hit within this window is found the first one for each side is determined. If both sides signal a valid hit the output VLD is set high and the time difference between the two is calculated and returned as an absolute value. Currently needs 5 clock cycles for the whole computation

Todo:

run at higher clock speed

Definition at line 111 of file delta_t_ac_top.vhd.

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Member Function Documentation

[Process]

select_for_each

( clk5x )

2-to-1 decoder for each channel

Definition at line 227 of file delta_t_ac_top.vhd.

  select_for_each : process(clk5x)
  begin
    if clk5x'event and clk5x = '1' then
      
      hit_irena <= '1';
      if S_irena1 = '1' then
        irena_int <= irena1(5 downto 0);
      elsif S_irena2 = '1' then
        irena_int <= irena2(5 downto 0);
      else
        irena_int <= (others => '0');
        hit_irena <= '0';
      end if;

      hit_ewa <= '1';
      if S_ewa1 = '1' then
        ewa_int <= ewa1(5 downto 0);
      elsif S_ewa2 = '1' then
        ewa_int <= ewa2(5 downto 0);
      else
        ewa_int <= (others => '0');
        hit_ewa <= '0';
      end if;

      hit_heinz <= '1';
      if S_heinz1 = '1' then
        heinz_int <= heinz1(5 downto 0);
      elsif S_heinz2 = '1' then
        heinz_int <= heinz2(5 downto 0);
      else
        heinz_int <= (others => '0');
        hit_heinz <= '0';
      end if;

      hit_andrej <= '1';
      if S_andrej1 = '1' then
        andrej_int <= andrej1(5 downto 0);
      elsif S_andrej2 = '1' then
        andrej_int <= andrej2(5 downto 0);
      else
        andrej_int <= (others => '0');
        hit_andrej <= '0';
      end if;

      hit_marko <= '1';
      if S_marko1 = '1' then
        marko_int <= marko1(5 downto 0);
      elsif S_marko2 = '1' then
        marko_int <= marko2(5 downto 0);
      else
        marko_int <= (others => '0');
        hit_marko <= '0';
      end if;

      hit_william <= '1';
      if S_william1 = '1' then
        william_int <= william1(5 downto 0);
      elsif S_william2 = '1' then
        william_int <= william2(5 downto 0);
      else
        william_int <= (others => '0');
        hit_william <= '0';
      end if;

      hit_harris <= '1';
      if S_harris1 = '1' then
        harris_int <= harris1(5 downto 0);
      elsif S_harris2 = '1' then
        harris_int <= harris2(5 downto 0);
      else
        harris_int <= (others => '0');
        hit_harris <= '0';
      end if;

      hit_helmut <= '1';
      if S_helmut1 = '1' then
        helmut_int <= helmut1(5 downto 0);
      elsif S_helmut2 = '1' then
        helmut_int <= helmut2(5 downto 0);
      else
        helmut_int <= (others => '0');
        hit_helmut <= '0';
      end if;
      
    end if;
  end process;

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Member Data Documentation

ADDSUB48 [Component]

Virtex-4 DSP Core.

Definition at line 192 of file delta_t_ac_top.vhd.

comparator4 [Component]

custom 4-input comparator core

Definition at line 203 of file delta_t_ac_top.vhd.

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The documentation for this class was generated from the following file:

• delta_t_ac_top.vhd