rio2mem Entity Reference
Contains all major design modules (RAMs, RIO, EMAC). More...
Inheritance diagram for rio2mem:
Collaboration diagram for rio2mem:
Architectures | |
| rio2mem_arc | Architecture |
| Contains all major design modules (RAMs, RIO, EMAC). More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
| work | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions operators for std_logic_vector type, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
| udp_addresses | Package <udp_addresses> |
| main_components | Package <main_components> |
| build_parameters | Package <build_parameters> |
Ports | |
| BCLK | in std_logic |
| 40 MHz in | |
| RIOCLK_1 | in std_logic |
| RocketIO reference clk1. | |
| RIOCLK_2 | in std_logic |
| RocketIO reference clk2. | |
| BCLK2X_P | in std_logic |
| 80 MHz pos | |
| BCLK2X_N | in std_logic |
| 80 MHz neg | |
| BCLK4X_P | in std_logic |
| 160 MHz pos | |
| BCLK4X_N | in std_logic |
| 160 MHz neg | |
| REFCLK_P | in std_logic |
| 200 MHz pos | |
| REFCLK_N | in std_logic |
| 200 MHz neg | |
| EMAC_CLK | in std_logic |
| 100 MHz | |
| DDRCLK | in std_logic |
| 160 MHz | |
| SATA_REF_CLK | in std_logic |
| SATA reference clk. | |
| SATA_LOGIC_CLK | in std_logic |
| SATA parallel clk. | |
| CLK_50 | in std_logic |
| 50 MHz | |
| CLK_HZ | in std_logic |
| 1 Hz | |
| XT_CLK_DET | in std_logic |
| Extern clock source for PLL detect. | |
| GP_ERR_FLAG | out std_logic |
| general purpose error flag | |
| MODE | out std_logic |
| 1 = expert mode, 0 = regular | |
| RESET | in std_logic |
| global reset | |
| RES_PC | out std_logic |
| reset from PC | |
| TRIG_PC | out std_logic |
| start buffer dump from PC | |
| STOP_PC | out std_logic |
| stop buffer dump from PC | |
| FORCE_PM | out std_logic |
| Post Mortem from PC. | |
| CALIBRATE_RIOS | in std_logic |
| send RocketIOs in calibration | |
| CHECK | out std_logic |
| RocketIO debug flag. | |
| LOCK_OUT | out std_logic |
| DDR-DCMs lock flag. | |
| MAC_LOCK | out std_logic |
| EMAC ready flag. | |
| SEND_ARP_ANN | in std_logic |
| Trigger sending of ARP annoncement. | |
| RIOS_READY | out std_logic |
| RocketIO ready flag. | |
| CAL_DONE | out std_logic |
| RocketIO calibration flag. | |
| SATA_OK | out std_logic |
| SATA ready flag. | |
| READ_OUT | in std_logic |
| start buffer dump | |
| READ_DONE | out std_logic |
| end of buffer dump flag | |
| READ_READY | in std_logic |
| Ready for read-out flag. | |
| READ_OVER | in std_logic |
| send end of buffer dump packet | |
| TRIGGER_INHIBIT_N | out std_logic |
| mask external triggers | |
| MAIN_FSM_ST | in std_logic_vector ( 7 downto 0 ) |
| Current state of main FSM. | |
| RXP_SATA_IN | in std_logic_vector ( 1 downto 0 ) |
| SATA P inputs. | |
| RXN_SATA_IN | in std_logic_vector ( 1 downto 0 ) |
| SATA N inputs. | |
| TXP_SATA_OUT | out std_logic_vector ( 1 downto 0 ) |
| SATA P outputs. | |
| TXN_SATA_OUT | out std_logic_vector ( 1 downto 0 ) |
| SATA N outputs. | |
| RXN_C_IE | in std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| RXP_C_IE | in std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| RXN_C_AH | in std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| RXP_C_AH | in std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| RXN_A_WM | in std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| RXP_A_WM | in std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| RXN_A_HH | in std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| RXP_A_HH | in std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| TXN_C_IE | out std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| TXP_C_IE | out std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| TXN_C_AH | out std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| TXP_C_AH | out std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| TXN_A_WM | out std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| TXP_A_WM | out std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| TXN_A_HH | out std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| TXP_A_HH | out std_logic_vector ( 1 downto 0 ) |
| RocketIO. | |
| MASK_IRENA | out std_logic |
| mask data input | |
| MASK_EWA | out std_logic |
| mask data input | |
| MASK_ANDREJ | out std_logic |
| mask data input | |
| MASK_HEINZ | out std_logic |
| mask data input | |
| MASK_MARKO | out std_logic |
| mask data input | |
| MASK_WILLIAM | out std_logic |
| mask data input | |
| MASK_HARRIS | out std_logic |
| mask data input | |
| MASK_HELMUT | out std_logic |
| mask data input | |
| OR_CH1 | out std_logic |
| logical OR of 4 RIOs | |
| OR_CH2 | out std_logic |
| logical OR of 4 RIOs | |
| cntrl0_DDR_A | out std_logic_vector ( 12 downto 0 ) |
| DDR address lines. | |
| cntrl0_DDR_BA | out std_logic_vector ( 1 downto 0 ) |
| DDR bank select. | |
| cntrl0_DDR_CKE | out std_logic |
| DDR clock enable. | |
| cntrl0_DDR_CS_N | out std_logic |
| DDR chip select. | |
| cntrl0_DDR_RAS_N | out std_logic |
| DDR row address strobe. | |
| cntrl0_DDR_CAS_N | out std_logic |
| DDR column address strobe. | |
| cntrl0_DDR_WE_N | out std_logic |
| DDR write enable. | |
| cntrl0_DDR_DM | out std_logic_vector ( 3 downto 0 ) |
| DDR data mask. | |
| cntrl0_DDR_CK | out std_logic |
| DDR clock pos. | |
| cntrl0_DDR_CK_N | out std_logic |
| DDR clock neg. | |
| cntrl0_DDR_DQ | inout std_logic_vector ( 31 downto 0 ) |
| DDR data. | |
| cntrl0_DDR_DQS | inout std_logic_vector ( 3 downto 0 ) |
| DDR data strobe. | |
| cntrl0_DDR2_A | out std_logic_vector ( 13 downto 0 ) |
| DDR2 address lines. | |
| cntrl0_DDR2_BA | out std_logic_vector ( 1 downto 0 ) |
| DDR2 bank select. | |
| cntrl0_DDR2_RAS_N | out std_logic |
| DDR2 row address strobe. | |
| cntrl0_DDR2_CAS_N | out std_logic |
| DDR2 column address strobe. | |
| cntrl0_DDR2_WE_N | out std_logic |
| DDR2 write enable. | |
| cntrl0_DDR2_RESET_N | out std_logic |
| DDR2 reset. | |
| cntrl0_DDR2_CS_N | out std_logic |
| DDR2 chip select. | |
| cntrl0_DDR2_ODT | out std_logic |
| DDR2 termination. | |
| cntrl0_DDR2_CKE | out std_logic |
| DDR2 clock enable. | |
| cntrl0_DDR2_DM | out std_logic_vector ( 7 downto 0 ) |
| DDR2 data mask. | |
| cntrl0_DDR2_CK | out std_logic |
| DDR2 clock pos. | |
| cntrl0_DDR2_CK_N | out std_logic |
| DDR2 clock neg. | |
| cntrl0_DDR2_DQ | inout std_logic_vector ( 63 downto 0 ) |
| DDR2 data. | |
| cntrl0_DDR2_DQS | inout std_logic_vector ( 7 downto 0 ) |
| DDR2 data strobe pos. | |
| cntrl0_DDR2_DQS_N | inout std_logic_vector ( 7 downto 0 ) |
| DDR2 data strobe neg. | |
| gmii_rx_clk | in std_logic |
| EMAC PHY RX clk. | |
| gmii_rx_dv | in std_logic |
| EMAC PHY RX valid. | |
| gmii_rx_er | in std_logic |
| EMAC PHY RX error. | |
| gmii_rxd | in std_logic_vector ( 0 to 7 ) |
| EMAC PHY RX data. | |
| mdio | inout std_logic |
| MDIO. | |
| mii_tx_clk | in std_logic |
| EMAC PHY TX clk. | |
| gmii_tx_en | out std_logic |
| EMAC PHY TX enable. | |
| gmii_tx_er | out std_logic |
| EMAC PHY TX error. | |
| gmii_txd | out std_logic_vector ( 0 to 3 ) |
| EMAC PHY TX data. | |
| MDC_0 | out std_logic |
| MDIO. | |
| phy_rst_n | out std_logic |
| EMAC PHY reset. | |
| TRIG_EXT | in std_logic |
| Trigger. | |
| GOTO_RD | out std_logic |
| readout flag | |
| CAPTURE | in std_logic |
| data taking flag | |
| SL_LFF | in std_logic |
| link full flag | |
| SL_LDOWN | in std_logic |
| link down flag | |
| SL_LRL | in std_logic_vector ( 3 downto 0 ) |
| return lines, not used! | |
| SL_UCLK | out std_logic |
| slink clock | |
| SL_UD | out std_logic_vector ( 31 downto 0 ) |
| data | |
| SL_URESET | out std_logic |
| reset | |
| SL_UTEST | out std_logic |
| test line | |
| SL_UWEN | out std_logic |
| write enable | |
| SL_UCTRL | out std_logic |
| control line | |
| SL_UDW | out std_logic_vector ( 1 downto 0 ) |
| data width | |
| BUSY | out std_logic |
| ROD Busy. | |
| ORBIT | in std_logic |
| ORBIT from LTP. | |
| BCR | in std_logic |
| Bunch Counter Reset. | |
| L1A | in std_logic |
| ATLAS Level-1 Accept. | |
| ECR | in std_logic |
| Event Counter Reset. | |
| TRIGGER_TYPE | in std_logic_vector ( 8 downto 1 ) |
| L1A Trigger Type. | |
| CTP | out std_logic_vector ( 9 downto 1 ) |
| CTP Inputs we provide. | |
| INJECT_PERM_1 | out std_logic |
| Injection Permit 1. | |
| INJECT_PERM_2 | out std_logic |
| Injection Permit 2. | |
| BEAM_PERM_1 | out std_logic |
| Beam Permit 1. | |
| BEAM_PERM_2 | out std_logic |
| Beam Permit 2. | |
| DSS_WARNING_1 | out std_logic |
| DSS Warning 1. | |
| DSS_WARNING_2 | out std_logic |
| DSS Warning 2. | |
| DSS_ABORT_1 | out std_logic |
| DSS Abort 1. | |
| DSS_ABORT_2 | out std_logic |
| DSS Abort 2. | |
| L1A_DISP | in std_logic |
| extended L1A pulse for status msg | |
| RIOERR | out std_logic |
| RocketIO error flag. | |
| RIOERR_TYPE | out std_logic_vector ( 7 downto 0 ) |
| RocketIO error indicator. | |
| SEND_ERR_MSG | in std_logic |
| start sending of error msg | |
| ERROR_CODE | in std_logic_vector ( 7 downto 0 ) |
| error code | |
Detailed Description
Contains all major design modules (RAMs, RIO, EMAC).In this Entity all major design parts are contained: both of the two big RAMs with their support logic & interface buffers, the EMAC for Ethernet connectability, the DAQ-RocketIOs, the ROD part with the SLINK interface & the time-window-coincidence logic module. Furthermore a FSM controlling the sequential read-out of the two big memories is also in here.
- Todo:
- RocketIO error checking
improve time-windows & coincidences
Definition at line 49 of file rio2mem.vhd.
Member Data Documentation
BCLK in std_logic [Port] |
BCLK2X_N in std_logic [Port] |
BCLK2X_P in std_logic [Port] |
BCLK4X_N in std_logic [Port] |
BCLK4X_P in std_logic [Port] |
BCR in std_logic [Port] |
BEAM_PERM_1 out std_logic [Port] |
BEAM_PERM_2 out std_logic [Port] |
BUSY out std_logic [Port] |
CAL_DONE out std_logic [Port] |
CALIBRATE_RIOS in std_logic [Port] |
CAPTURE in std_logic [Port] |
CHECK out std_logic [Port] |
CLK_50 in std_logic [Port] |
CLK_HZ in std_logic [Port] |
cntrl0_DDR2_A out std_logic_vector ( 13 downto 0 ) [Port] |
cntrl0_DDR2_BA out std_logic_vector ( 1 downto 0 ) [Port] |
cntrl0_DDR2_CAS_N out std_logic [Port] |
cntrl0_DDR2_CK out std_logic [Port] |
cntrl0_DDR2_CK_N out std_logic [Port] |
cntrl0_DDR2_CKE out std_logic [Port] |
cntrl0_DDR2_CS_N out std_logic [Port] |
cntrl0_DDR2_DM out std_logic_vector ( 7 downto 0 ) [Port] |
cntrl0_DDR2_DQ inout std_logic_vector ( 63 downto 0 ) [Port] |
cntrl0_DDR2_DQS inout std_logic_vector ( 7 downto 0 ) [Port] |
cntrl0_DDR2_DQS_N inout std_logic_vector ( 7 downto 0 ) [Port] |
cntrl0_DDR2_ODT out std_logic [Port] |
cntrl0_DDR2_RAS_N out std_logic [Port] |
cntrl0_DDR2_RESET_N out std_logic [Port] |
cntrl0_DDR2_WE_N out std_logic [Port] |
cntrl0_DDR_A out std_logic_vector ( 12 downto 0 ) [Port] |
cntrl0_DDR_BA out std_logic_vector ( 1 downto 0 ) [Port] |
cntrl0_DDR_CAS_N out std_logic [Port] |
cntrl0_DDR_CK out std_logic [Port] |
cntrl0_DDR_CK_N out std_logic [Port] |
cntrl0_DDR_CKE out std_logic [Port] |
cntrl0_DDR_CS_N out std_logic [Port] |
cntrl0_DDR_DM out std_logic_vector ( 3 downto 0 ) [Port] |
cntrl0_DDR_DQ inout std_logic_vector ( 31 downto 0 ) [Port] |
cntrl0_DDR_DQS inout std_logic_vector ( 3 downto 0 ) [Port] |
cntrl0_DDR_RAS_N out std_logic [Port] |
cntrl0_DDR_WE_N out std_logic [Port] |
CTP out std_logic_vector ( 9 downto 1 ) [Port] |
DDRCLK in std_logic [Port] |
DSS_ABORT_1 out std_logic [Port] |
DSS_ABORT_2 out std_logic [Port] |
DSS_WARNING_1 out std_logic [Port] |
DSS_WARNING_2 out std_logic [Port] |
ECR in std_logic [Port] |
EMAC_CLK in std_logic [Port] |
ERROR_CODE in std_logic_vector ( 7 downto 0 ) [Port] |
FORCE_PM out std_logic [Port] |
gmii_rx_clk in std_logic [Port] |
gmii_rx_dv in std_logic [Port] |
gmii_rx_er in std_logic [Port] |
gmii_rxd in std_logic_vector ( 0 to 7 ) [Port] |
gmii_tx_en out std_logic [Port] |
gmii_tx_er out std_logic [Port] |
gmii_txd out std_logic_vector ( 0 to 3 ) [Port] |
GOTO_RD out std_logic [Port] |
GP_ERR_FLAG out std_logic [Port] |
ieee library [Library] |
INJECT_PERM_1 out std_logic [Port] |
INJECT_PERM_2 out std_logic [Port] |
L1A in std_logic [Port] |
L1A_DISP in std_logic [Port] |
LOCK_OUT out std_logic [Port] |
MAC_LOCK out std_logic [Port] |
MAIN_FSM_ST in std_logic_vector ( 7 downto 0 ) [Port] |
MASK_ANDREJ out std_logic [Port] |
MASK_EWA out std_logic [Port] |
MASK_HARRIS out std_logic [Port] |
MASK_HEINZ out std_logic [Port] |
MASK_HELMUT out std_logic [Port] |
MASK_IRENA out std_logic [Port] |
MASK_MARKO out std_logic [Port] |
MASK_WILLIAM out std_logic [Port] |
MDC_0 out std_logic [Port] |
mdio inout std_logic [Port] |
mii_tx_clk in std_logic [Port] |
MODE out std_logic [Port] |
OR_CH1 out std_logic [Port] |
OR_CH2 out std_logic [Port] |
ORBIT in std_logic [Port] |
phy_rst_n out std_logic [Port] |
READ_DONE out std_logic [Port] |
READ_OUT in std_logic [Port] |
READ_OVER in std_logic [Port] |
READ_READY in std_logic [Port] |
REFCLK_N in std_logic [Port] |
REFCLK_P in std_logic [Port] |
RES_PC out std_logic [Port] |
RESET in std_logic [Port] |
RIOCLK_1 in std_logic [Port] |
RIOCLK_2 in std_logic [Port] |
RIOERR out std_logic [Port] |
RIOERR_TYPE out std_logic_vector ( 7 downto 0 ) [Port] |
RIOS_READY out std_logic [Port] |
RXN_A_HH in std_logic_vector ( 1 downto 0 ) [Port] |
RXN_A_WM in std_logic_vector ( 1 downto 0 ) [Port] |
RXN_C_AH in std_logic_vector ( 1 downto 0 ) [Port] |
RXN_C_IE in std_logic_vector ( 1 downto 0 ) [Port] |
RXN_SATA_IN in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_A_HH in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_A_WM in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_C_AH in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_C_IE in std_logic_vector ( 1 downto 0 ) [Port] |
RXP_SATA_IN in std_logic_vector ( 1 downto 0 ) [Port] |
SATA_LOGIC_CLK in std_logic [Port] |
SATA_OK out std_logic [Port] |
SATA_REF_CLK in std_logic [Port] |
SEND_ARP_ANN in std_logic [Port] |
SEND_ERR_MSG in std_logic [Port] |
SL_LDOWN in std_logic [Port] |
SL_LFF in std_logic [Port] |
SL_LRL in std_logic_vector ( 3 downto 0 ) [Port] |
SL_UCLK out std_logic [Port] |
SL_UCTRL out std_logic [Port] |
SL_UD out std_logic_vector ( 31 downto 0 ) [Port] |
SL_UDW out std_logic_vector ( 1 downto 0 ) [Port] |
SL_URESET out std_logic [Port] |
SL_UTEST out std_logic [Port] |
SL_UWEN out std_logic [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 26 of file rio2mem.vhd.
std_logic_arith package [Package] |
std_logic_unsigned package [Package] |
unsigned functions operators for std_logic_vector type, see file
Definition at line 30 of file rio2mem.vhd.
STOP_PC out std_logic [Port] |
TRIG_EXT in std_logic [Port] |
TRIG_PC out std_logic [Port] |
TRIGGER_INHIBIT_N out std_logic [Port] |
TRIGGER_TYPE in std_logic_vector ( 8 downto 1 ) [Port] |
TXN_A_HH out std_logic_vector ( 1 downto 0 ) [Port] |
TXN_A_WM out std_logic_vector ( 1 downto 0 ) [Port] |
TXN_C_AH out std_logic_vector ( 1 downto 0 ) [Port] |
TXN_C_IE out std_logic_vector ( 1 downto 0 ) [Port] |
TXN_SATA_OUT out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_A_HH out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_A_WM out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_C_AH out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_C_IE out std_logic_vector ( 1 downto 0 ) [Port] |
TXP_SATA_OUT out std_logic_vector ( 1 downto 0 ) [Port] |
unisim library [Library] |
vcomponents package [Package] |
XT_CLK_DET in std_logic [Port] |
The documentation for this class was generated from the following file:
